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STV2310
Multistandard TV Digital Video Decoder with Adaptive Comb Filter and RGB/YCrCb Input
DATASHEET
MAIN FEATURES
Worldwide TV Standards Compatible Automatic NTSC/PAL/SECAM Digital Chroma Decoder NTSC/PAL Adaptive 4H/2D Comb Filter VBI Data Slicer for Teletext, Closed Caption, WSS and other systems Analog RGB/Fast Blanking Capture and Insertion in YCrCb Output Flow (SCART legacy) Analog YCrCb inputs with Tint Control 10-bit, 30-MSPS A/D Converter for Y/CVBS input 8-bit, 30-MSPS A/D Converter for C and RGB/ CrCb inputs Hue control and automatic flesh control for NTSC CVBS/YC signals Programmable Horizontal Scaling (x0.25 to x4 Scaling Factor) and Panorama Vision Copy-Protection System compatible H and V Synchronisation Processing that is robust to non-standard sources such as VCR, and to weak and noisy signals 8-bit Pixel Output Interface Line-Locked ITUR BT_656/601 or square pixel YCrCb outputs Single System Clock for all Video Input Formats Two-wire IC Bus Interface up to 400 kHz Typical Power Consumption: 550 mW Power Supply: 1.8 V and 3.3 V The STV2310 is a high-quality front-end video circuit for processing all analog NTSC/PAL/SECAM standards into a 4:2:2 YCrCb digital video format ,as well as conventional analog RGB or YCrCb signals. The STV2310 is programmable through an IC interface. The STV2310 provides a cost-effective solution for digitized TV, LCD TV/monitors, digital TV, STB, video surveillance/security, video conferencing, video capturing devices and PC video card. It can be used as a stand-alone chip working with third-party products, as a companion chip to the TV processor STV3500, STV3600 for digitized 100-Hz/ ProScan CRT TVs, or as a companion chip to the TV processor STV3550 for LCD-TVs.
TQFP64 10x10x1.4 mm (Thin Quad Flat Package) ORDER CODE: STV2310SD/SDT TQFP64 14x14x1.4 mm (Thin Quad Flat Package) ORDER CODE: STV2310D/DT
December 2004
Revision 3.1
eDocs No. CD00003507
STMicroelectronics Confidential
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C
CVBS1/Y CVBS2/Y
Adaptive Luminance VBI Data Cr Cb Tint Data Selection and Output 4H/
Analog to Digital Conver sion
Luma Chro ma Sepa rator
Fully Automatic PAL/NTSC/ SECAM Line Form at Conve rter and Outpu
R/Cr G B/Cb
I2C Bus Clock Gener
Analog to Digital
YCrCb[7:0] Clock HSYNC VSYNC Field
Figure 1: STV2310 Block Diagram
Synchronizatio n
STV2310
STV2310
STV2310
Table of Contents
Chapter 1 Chapter 2
2.1 2.2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Allocation and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pinout Diagram ................................................................................................................... 9 Pin Descriptions ................................................................................................................. 9
Chapter 3
3.1
Default Setup At Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
System Clock Generation .................................................................................................. 13
Chapter 4
4.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Analog Input Stage ............................................................................................................. 14
4.1.1 4.1.2 General Description ..............................................................................................................................14 Programming ........................................................................................................................................16
4.2
Synchronization and Monitoring Unit ................................................................................. 16
4.2.1 4.2.2 General Description ..............................................................................................................................16 Programming ........................................................................................................................................17
4.3 4.4
Input Sample Rate Conversion .......................................................................................... 18
4.3.1 General Description ..............................................................................................................................18
Luminance and Chrominance Separation .......................................................................... 19
4.4.1 4.4.2 General Description ..............................................................................................................................19 Programming ........................................................................................................................................19
4.5 4.6 4.7
Standard Research Sequence Programming .................................................................... 21 Standard Identification ....................................................................................................... 22 Chroma Demodulation ....................................................................................................... 22
4.7.1 4.7.2 General Description ..............................................................................................................................22 Programming ........................................................................................................................................23
4.8
Soft Mixer ........................................................................................................................... 23
4.8.1 4.8.2 General Description ..............................................................................................................................23 Programming ........................................................................................................................................24
4.9
Output Scaler and Format Converter ................................................................................. 24
4.9.1 4.9.2 General Description ..............................................................................................................................24 Programming ........................................................................................................................................26
4.10
RGB Insertion ..................................................................................................................... 27
4.10.1 4.10.2 General Description ..............................................................................................................................27 Programming ........................................................................................................................................28
4.11
Analog YCrCb Mode .......................................................................................................... 28
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STV2310
4.11.1 4.11.2 General Description ............................................................................................................................. 28 Programming ....................................................................................................................................... 28
4.12
Output FIFO and Line-locked Ouput Pixel Clock Generator ..............................................29
4.12.1 4.12.2 4.12.3 4.12.4 4.12.5 4.12.6 4.12.7 General Description ............................................................................................................................. 29 Output Data ......................................................................................................................................... 29 Insertion of Ancillary Data .................................................................................................................... 39 Line-Locked Output Pixel Clock Generation ........................................................................................ 40 Alternate Functions: Bus Extensions ................................................................................................... 40 Output Code Clipping ........................................................................................................................... 40 Programming ....................................................................................................................................... 40
4.13
VBI Data Slicing and Insertion ............................................................................................41
4.13.1 4.13.2 VBI Formatting Features ...................................................................................................................... 42 Data Output Format (DOF) .................................................................................................................. 43
4.14
IC Bus Specifications ........................................................................................................52
Chapter 5
5.1 5.2 5.3 5.4 5.5
Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Register Map .....................................................................................................................54 Non-VBI Control Register Descriptions ..............................................................................58 VBI Control Register Descriptions ......................................................................................86 Acknowledge Registers ......................................................................................................95 Status Registers .................................................................................................................96
Chapter 6
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Absolute Maximum Ratings .............................................................................................100 Thermal Data ...................................................................................................................100 Operating Conditions .......................................................................................................100 CVBS/Y/C Analog Inputs ..................................................................................................100 R/G/B and Cr/Cb Inputs ....................................................................................................101 FB Input ...........................................................................................................................102 Analog-to-Digital Converter (ADC) ..................................................................................102 Analog Reference Levels .................................................................................................102 YCrCb, Hsync, Vsync, Field and PLL Lock Outputs .........................................................102 Clock Data Output ...........................................................................................................103 CLKSEL, TST_MODE, NRESET and I2CADD Inputs .....................................................103 Main Clock Characteristics ..............................................................................................103 Horizontal/Vertical Synchronization Block .......................................................................105 Chroma Block ..................................................................................................................105 IC Bus Characteristics ...................................................................................................105
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STV2310 Chapter 7
7.1 7.2
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
TQFP64 14x14 Package ................................................................................................. 107 TQFP64 10x10 Package ................................................................................................. 108
Chapter 8
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
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General Description
STV2310
1
General Description
The STV2310 is a high-quality video front-end circuit for processing all analog standards into a digitalized 4:2:2 YCrCb video format. It processes NTSC/PAL/SECAM CVBS signals, as well as conventional analog RGB or YCrCb signals. This circuit outputs demodulated chrominance, in-phased luminance and sliced Vertical Blanking Interval (VBI) data for the most common services such as Teletext, Closed Caption, WSS, VPS, Gemstar. The STV2310 does not need an external synchronization system. It extracts all necessary synchronization signals from CVBS or Y signals, and delivers the horizontal, vertical and frame signals either on dedicated pins or embedded into the digital bit stream. It features automatic standard recognition and automatic selection of the optimal Y/C separation algorithm according to the standard and has extensive output scaling capabilities. The STV2310 chip includes an analog RGB capture feature and programmable automatic mixing with the main picture digital output. 8-bit ITU-R BT.601/656 and Square Pixel output standards are supported. The STV2310 provides a cost-effective solution for digitized TV, LCD TV/monitors, digital TV, STB, video surveillance/security, video conferencing, video capturing devices and PC video card. It can be used as a stand-alone chip working with third-party products, as a companion chip to the TV processor STV3500, STV3600 for digitized 100-Hz/ProScan CRT TVs, or as a companion chip to the TV processor STV3550 for LCD-TVs. All sub-level blocks operate at the frequency used as a sampling frequency (fS) for the five embedded A/D converters. This free-running clock is called the system clock (fS) and is provided
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STV2310
General Description
either by an embedded crystal oscillator or an external clock generator (27 MHz).The only exception is the output stage which operates at the line-locked output pixel clock frequency.
Figure 2: Architectural Block Diagram
CVBS1/Y CVBS2/Y C
Analog Input Stage
R/Cr G B/Cb FB
Input SRC
Luma Chroma Separator 4H/2D Comb Filter
Standard Identifier & Chroma Demodulator
PAL/NTSC/SECAM Adaptive Luminance Delay
Soft Mixer
RGB/CrCb Processing CrCb Tint RGB Gain FB Delay IC Interface System Clock Generation
27 MHz PLLLOCK/IRQ
Format Converter & Output Scaler
Video Correction
SDA SCL
VBI Slicer Synchronization and Monitoring Unit Output FIFO
Line-locked Output Pixel Clock
CLKSEL CLKXTH
YCrCb[7:0] HSYNC VSYNC Field Line-locked Ouput Pixel Clock
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General Description
Figure 3: Application Block Diagram
1.8 VANA 150 470 1.8 VANA
STV2310
1 CVBS1/Y CVBS2/Y 63 2 57 56
64
60
59
58
62
61
11
12 4 1.8 VANA
VREF
ADC
10
5
7 8
3.3 VANA
1.8 VANA
C
3 45 47
ADC SHIELD 8 8 ADC 8
14 15
3.3 VANA
R_CR 51 G 52 53 B_CB Optional FB 1.8 VANA 48
Chroma/Luma Processing
VBI Data Slicer
17 18 24
1.8 VANA
8
3.3 VOUT
23 Digital Core
28 27 26 25 Y Cr Cb Output 22 21 20 19
46 49 50
Data Formatting
1.8 VANA 3.3 V
54 55
SCL SDA 3.3 VANA
10 9
Synchronization and Monitoring
33 34 35
HSYNC VSYNC FIELD PLLLOCK CLK_DATA
13 16
NRESET I2CADD*
Digital Core
32 31
Time Base
40 36 NC 38 1.8 VANA CLKSEL 37 39 44 42 27 MHz 41 43 6
29 30 1.8 VOUT
CLKXTM TST_MODE
1.8 VANA
* Possible alternate IC address. See Section
5.1: Register Map on page 54.
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STV2310
Pin Allocation and Description
2
2.1
Pin Allocation and Description
Pinout Diagram
Figure 4: 64-Pin 14 x 14 TQFP Package Pinout
CC18_CVBS VBS2_Y DD18_CORE S T_MODE DD18_CORE S DA CL DD18_CORE S RESET DD33_IO S_IO CADD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND_CVBS CVBS1_Y REFM_CVBS REFP_CVBS VIDEO_OUT VIDEOCOMM ADCIN VCC33_IO GND_IO GND_DIG VCC18_DIG B_CB G R_CR GND_RGB VCC18_RGB
REFM_RGB REFP_RGB FB SHIELD CLKSEL CLKXTM XTALIN_CLKXTP XTALOUT GND_CLK VCC18_CLK VCC18_SUB GND_SUB NC FIELD VSYNC HSYNC
2.2
Pin Descriptions
Table 1: Power Supply Pins (page 1 of 2)
Pin
Analog 1 36 37 38 39
Pin Name
Pin Description
VCC18_CVBS NC GND_SUB VCC18_SUB VCC18_CLK
1.8 V Analog Voltage Supply for Analog Input Stage Not connected Analog Ground Supply (Substrate Polarization) 1.8 V Analog Voltage Supply (Output and Pin Isolation layer) 1.8 V Analog Voltage Supply for Clock Generator
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Pin Allocation and Description
Table 1: Power Supply Pins (page 2 of 2) Pin
40 45 49 50 54 55 56 57 64 Digital 4 5 7 8 11 12 14 15 17 18 23 24 29 30 VDD18_CORE VSS VDD18_CORE VSS VDD18_CORE VSS VDD33_IO VSS_IO VDD18_CORE VSS VSS_IOOUT VDD33_OUT VDD18_OUT VSS_OUT 1.8 V Digital Voltage Supply (Digital Core) Digital Ground Supply (Digital Core) 1.8 V Digital Voltage Supply (Digital Core) Digital Ground Supply (Digital Core) 1.8 V Digital Voltage Supply (Digital Core) Digital Ground Supply (Digital Core) 3.3 V I/O Voltage Supply (Digital Core) I/O Ground Supply 1.8 V Digital Voltage Supply (Digital Core) Digital Ground Supply (Digital Core) Output Ground Supply (Output Stage) 3.3 V Output Voltage Supply (Output Stage) 1.8 V Digital Voltage Supply (Output Stage) Digital Ground Supply (Output Stage)
STV2310
Pin Name
GND_CLK SHIELD VCC18_RGB GND_RGB VCC18_DIG GND_DIG GND_IO VCC33_IO GND_CVBS
Pin Description
Analog Ground Supply for Clock Generator Guard Ring (Analog Input Stage) To be connected to Analog Ground Supply 1.8 V Analog Voltage Supply (RGB) Analog Ground Supply (RGB) 1.8 V Analog Voltage Supply (Analog Input Stage) Analog Ground Supply (Analog Input Stage) Analog Ground Supply (Analog Input Stage) 3.3 V Analog Voltage Supply (Analog Input Stage) Analog Ground Supply (Analog Input Stage)
Table 2: Analog Pins (page 1 of 2) Pin
2 3 46 47 48 51 52 53
Pin Name
CVBS2_Y C FB REFP_RGB REFM_RGB R_CR G B_CB
Pin Description
CVBS or Y Input 2 (Selected by programming) Chroma Input (Y/C inputs used for S-Video) (Selected by programming) Fast Blanking Input (To be used only when R_CR, G, and B_CB inputs are connected) Positive Reference Voltage for RGB ADCs Negative Reference Voltage for RGB ADCs R Input for RGB Insertion. Cr Input for Analog YCrCb mode. G Input for RGB Insertion. B Input for RGB Insertion. Cb Input for Analog YCrCb mode.
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STV2310
Table 2: Analog Pins (page 2 of 2) Pin
58 59 60 61 62 63
Pin Allocation and Description
Pin Name
ADCIN VIDEOCOMM VIDEO_OUT REFP_CVBS REFM_CVBS CVBS1_Y
Pin Description
CVBS ADC Input (To be connected to Anti-Aliasing Filter output) CVBS Anti-Aliasing Filter Reference Voltage Video Analog Front-end Multiplexer Output for external filtering Positive Reference Voltage for CVBS and Chroma ADCs Ground CVBS and Chroma ADCs CVBS or Y Input 1 (Selected by programming)
Table 3: Output Pins Pin
19 20 21 22 25 26 27 28 31 32
Pin Name
YCRCB7 YCRCB6 YCRCB5 YCRCB4 YCRCB3 YCRCB2 YCRCB1 YCRCB0 CLK_DATA PLLLOCK/IRQ
Type
O O O O O O O O O O Digital Video Output 7 Digital Video Output 6 Digital Video Output 5 Digital Video Output 4 Digital Video Output 3 Digital Video Output 2 Digital Video Output 1 Digital Video Output 0
Pin Description
Output Pixel Clock, active edge is programmable Output PLL Lock Signal Alternate Function 1: OUTBUS[0] Bus extension Alternate Function 2: Interrrupt Request (IRQ) Horizontal Synchronization Pulse Output Alternate Function: OUTBUS[1] Bus extension Vertical Synchronization Pulse Output Alternate Function: OUTBUS[2] Bus extension Field (Parity) Output Signal Alternate Function: OUTBUS[3] Bus extension
33 34 35
HSYNC VSYNC FIELD
O O O
Table 4: Clock Signal Pins Pin
41 42
Pin Name
XTALOUT XTALIN_CLKXTP Crystal Pad Oscillator Output Crystal Pad Oscillator Input
Pin Description
Alternate Function: Differential Clock input 43 44 CLKXTM CLKSEL Differential Clock input (To be used in conjunction with CLKXTP) OV: Differential Clock input active (CLKXTM, CLKXTP 3.3V: Crystal Pad Oscillator active (XTALOUT, XTALIN)
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Pin Allocation and Description
Table 5: Configuration Pins Pin
6 9 10 13 16
STV2310
Pin Name
TST_MODE SDA SCL NRESET I2CADD I
Type
To be Connected to Ground IC Bus Data IC Bus Clock Active Low Reset
Pin Description
I/O I/O I I
0V: 86h/87h and output pad active at Reset 3.3V: 8Eh/8Fh and output pad high impedance state at Reset
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STV2310
Default Setup At Reset
3
Default Setup At Reset
The default configuration at reset is:

CVBS1_ input active Fast Blanking input for RGB insertion enable Automatic Standard Recognition of NTSC/PAL/SECAM Comb filter enable Data slicer enable Output ITU_R BT. 656/601 Output clock CLK_DATA rising edge active PLL lock, HSYNC, VSYNC, FIELD primary functions enable Output pads active when Pin 16 connected to ground Output pads high impedance state when pin 16 connected to 3.3V Automatic HPLL time constant selection
For more detailed reset configuration descriptions, refer to Chapter 5: Register List.
3.1
System Clock Generation
The STV2310 clock is either provided by an internal 27-MHz crystal oscillator connected to pins XTALIN_CLKXTP and XTALOUT, or imported in Differential mode from an external device such as the STV3500 and connected to the XTALIN_CLKXTP and CLKXTM pins.
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Functional Description
STV2310
4
4.1
4.1.1
Functional Description
Analog Input Stage
General Description
The Analog Input Stage provides the interface between the incoming video signals and the Analogto-Digital Converters (ADC) using Clamp and Automatic Gain Control (AGC) stages to fit the analog signals to the ADC range. Several video sources are processed in this stage:

CVBS signals from a broadcast signal or the SCART connector. S-Video (Y/C) signals coming from an external video source (VCR, DVD, STB). RGB signals with Fast Blanking (FB) input coming from the SCART connector. Analog YCrCb signals coming from a DVD player (1H interlaced).
Figure 5: Analog Input Stage Functional Block Diagram
Anti-Aliasing Filter ADC Bias 1 PGA 6 dB 10-bit ADC
CVBS1/Y CVBS2/Y
Analog Switch
CVBS Clamp Control
Composite and Luminance Input Channels Chroma Bias C Chrominance Input Channel ADC Bias 2 R_CR Controller G Controller B_CB B_CB Clamp Control G Clamp Control
8-bit ADC
Controller
R_CR Clamp Control
8-bit ADC 8-bit ADC 8-bit ADC 6-bit Interpolator
FB RGB and Fast Blanking Input Channels
The CVBS/Y signal from the selected input channel goes through an automatic clamp and a Programmable Gain Amplifier (PGA) circuit. The clamping circuit automatically adjusts the black level to a programmable A/D output digital code. The clamp voltage is stored on the input coupling capacitor (22 nF, external to the STV2310). The PGA automatically adjusts the input signal
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STV2310
Functional Description
magnitude by 6 dB in 63 logarithmic steps to the optimal range of the A/D Converter. The video signal then goes through an external anti-aliasing filter before reaching the A/D Converter. The A/D Converter dedicated to the CVBS/Y channel has a 10-bit resolution. The A/D Converters dedicated to the C, R_Cr, G and B_Cb channels have an 8-bit resolution.
Figure 6: Anti-Aliasing FIlter for CVBS Input Signals
150 VIDEOOUT ADC
470 VIDEOCOMM
Two independent CVBS sources can be connected to the STV2310. To process S-Video signals, the luma signal is connected to one of the CVBS inputs and the chroma signal is connected to the C input. RGB signals are directly connected to the three separate inputs (R_Cr, G and B_Cb). For Analog YCrCb signals, the luma signal is connected to one of the CVBS inputs, the Cr signal is connected to the R_CR input and the Cb signal is connected to the B_CB input. For S-Video signals, the Y (luminance) signal is connected to the selected CVBS input. The analog C (chrominance) input includes a bias and fixed gain circuit. The C signal is digitized by an 8-bit A/ D Converter. It is recommended that an external anti-aliasing filter be added before the C input.
Figure 7: Anti-Aliasing FIlter for Chroma Input Signals
C_AV 22 nF
C
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Functional Description
STV2310
Analog R_PR, G and B_PB signals are clamped to the black level during the back porch period. These signals are digitized by a triple 8-bit A/D converter. It is recommended that an external antialiasing filter be added before each channel input.
Figure 8: Anti-Aliasing FIlter for R_PR, G and B_PB Input Signals
R/Cr G B/Cb
22 nF
R_PR G B_PB
The analog insertion (Fast Blanking) signal is sliced and sent to a shaper, controlling the soft switching between the analog R, G and B signals and the decoded main picture CVBS stream. All reference voltages required by the A/D Converter are internally generated. Only two pairs of reference levels, REFP and REFM must be decoupled externally (REFP_CVBS and REFM_CVBS, REFP_RGB and REFM_RGB ).
4.1.2
Programming
The channel for the desired CVBS signal source is selected by the CVBSMUX bit in the DDECCONT0 register. The AGC and clamp mechanisms are described in Section 4.2.
4.2
4.2.1
Synchronization and Monitoring Unit
General Description
The STV2310 system clock sampling frequency is provided by a free-running embedded crystal oscillator or an external clock generator. The nominal value of this sampling frequency is 27 MHz and is independent of any input TV standard. Synchronization data (horizontal and vertical sync signals) is extracted from the video signal. After a low pass stage removing all high frequency information and noise, the video signal is sent to a synchronization slicer. Then the horizontal and vertical pulses are separated to generate the Hsync and Vsync pulses. The extracted Hsync pulses are sent to the horizontal PLL (HPLL) in order to filter the jitter. The HPLL has an adaptive time constant with noise level and other operating conditions. It provides an easy lock even in difficult conditions and performs the skew extraction. Using this data, skew correction on the data stream is performed by the output scaler. This PLL can hold a frequency range of 8% of the H frequency. A second PLL, associated with the output FIFO, is used to perform the line-locked clock generation from which the output HSYNC and VSYNC pulses are obtained by synchronous division. A vertical sync processor is used to generate the output Vsync pulse, synchronous to the incoming CVBS signal. This processor is able to automatically detect 50 Hz/60 Hz standards. In the event of missing pulses, the Vsync processor replaces the missing pulse by inserting a V-pulse at the end of the 50 Hz or 60 Hz windows. If an input video signal (CVBS or S-Video) is not detected, the sync processor operates in Freerunning mode.
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STV2310
Functional Description
The Output Sync Pulse (H, V and F) can be embedded in the digital output stream, according to the ITU_R BT_656/601 format, using the EAV and SAV codes. The Output Sync Pulse can also be delivered on dedicated external pins (33, 34, 35). These pins can be used specifically if the output sync pulses are no longer compliant with the ITU_R BT_656/601 format, as non-interlaced pictures or signals from a non-standard source (VCR). See Section 4.12.2.1 and Section 4.12.2.2 for more information.
4.2.2
Programming
The circuit can function in Automatic mode or use a programmable HPLL time constant. Automatic mode is selected by default. In this case the STV2310 automatically adapts the time constant to the reception conditions. In the case of unstable sources (such as VCRs) the circuit uses a special user-programmable VCR time constant. This HPLL time constant's proportional gain is selected in the HSYN_GP[7:0] bits in the DDECCONT26 register. The value for the integral gain is selected in the HSYN_GI[7:0] bits in the DDECCONT27 register. These bits also define the programmable time constant when the HTIMECSTSEL bit is reset in the DDECCONT22 register (Automatic mode disabled). To be automatically selected, the VCR time constant requires that the noise level be below the noise threshold selected by the NOISE_THRESHOLD[2:0] bits in the DDECCONT25 register. The Vsync search and initial Free-running modes are selected by the 5060MODE[1:0] bits in the DDECCONT0 register. The (fluctuating) average sync bottom and blanking level values, based on the Hsync Pulse Bottom Period and Composite Video Burst Period identification data, are necessary in turn to perform the clamp correction on the CVBS signal in the analog domain. (See Figure 9.) The clamp level is programmed by the BLANKMODE[1:0] bits in the DDECCONT1 register. The Active Input Video Period and small amplitude signals for the Active Input Video Period levels which control the gain level of the AGC are programmed in the ACTITH[1:0] and SMHITH[1:0] bits (respectively) in the DDECCONT16 register. The CVBS saturation threshold is programmed in the SATLMTPT[1:0] and SATLMTLN[1:0] bits of the DDECCONT16 register in the event of a high level of chroma demodulation. It is expressed as a number of samples per field (when, according to the algorithm, the number of samples is reached, the gain is decreased). Output mode can be forced to 50 Hz or 60 Hz by 5060MODE[1:0] bits in the the DDECCONT00 register. To output a non-interlaced image, the chip must be set in direct parity mode by the DIRECTPARITY bit in the DDECCONT1F register.
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Functional Description
STV2310
The external HSync pulse can be synchronised to the End of Active Video (EAV) and the Start of Active Video (SAV) pulses, or initialized according to the usual analog H/V pulse using the HSYNC_SAV bit in the DDECCONT25 register.
Figure 9: AGC Flowchart Points/Line Threshold 0 to 65 32 8 9 5 Line Threshold
Code CVBS Saturation Threshold Luma Saturation Threshold Luma Low Signal Detection Threshold 1020 807 + 8x 772 + 8x
256/244 Small Amplitude Signal for Hsync Pulse Bottom Period Hsync Pulse Bottom Period
30 18 0
108 16
220 9
4.3
4.3.1
Input Sample Rate Conversion
General Description
An Input Sample Rate Converter (ISRC) converts the acquisition pixel rate to a clock domain virtually locked to the color subcarrier. This ISRC is controlled by a subcarrier phased-locked loop (Chroma PLL). This enables comb filtering and chroma demodulation to be carried out on various subcarrier frequencies using the same system clock sampling frequency. The Input SRC uses the data provided by the front-end ADCs to process both the CVBS and C flows (in the event of separated Y/C inputs, the CVBS flow = Y flow). The same processing is applied to the CVBS and C data. When the input video standard has been identified, its subcarrier frequency (fSC) is known and the Chroma PLL is locked. The Input SRC transforms the input data captured at the 27-MHz system clock sampling frequency (fS) to the subcarrier clock domain frequency (4 x fSC).
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STV2310
Functional Description
The practical value of the 4 x fSC frequency depends on the actual input TV standard.
4.4
4.4.1
Luminance and Chrominance Separation
General Description
The Y/C Separator separates the chrominance (C) component from the composite signal which also includes the luminance (Y), synchronization and color burst (subcarrier) components. In normal operation (NTSC and PAL standards), this is done through comb or notch filtering which relies on the correlation of consecutive lines. For SECAM inputs, a Chroma Bandpass/Trap filter system is required. If an S-Video input is selected, Y/C separation is not required and the Y/C Separator operates in Bypass mode. Y/C delay adjustment can be done with both pixel and subpixel accuracy.
4.4.2
Programming
Once the samples processed by the input SRC have been stored in RAM, the type of input signal (Y/C or CVBS) must be specified before the chroma component can be separated from the CVBS input signal. This is done by setting the SVIDEOSEL bit in the DDECCONT0 register. The Y/C separator block can either operate in auto-adaptive mode (Default mode) or Forced Separation mode (notch). This operating mode is selected by the COMB_MODE bit in the DDECCONT18 register:

Chroma Bandpass/Trap filtering is forced Adaptative Comb Filtering mode is forced. (This applies to PAL/NTSC signals only. SECAM signals remain processed by Chroma Bandpass/Trap filter)
The notch filter width used in the Y/C separation can be adjusted from narrow to wide by the BW_SEL[2:0] bits in the DDECCONT18 register. Luma Chroma delay can be adjusted by the DEM_YC_DELAY[3:0] bits in the DDECCONT15 register and DDECCONT1A register, bit [5:0].
Figure 10: SECAM Trap Filter Frequency Response
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Functional Description
Figure 11: Notch Filter - Narrow Group
STV2310
Figure 12: Notch Filter - Wide Group
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STV2310
Functional Description
4.5
Standard Research Sequence Programming
The chroma signal is sent to the Standard Identifier and Chroma Demodulator. The Standard Identifier performs an automatic recognition sequence for one of the following standards.
Table 6: TV Standards Chroma Standard
PAL B,D,G,H,I SECAM NTSC M PAL M PAL N NTSC 4.43 No Standard1 No Standard1
Subcarrier Frequency
4.4336 MHz 4.406 MHz (foR) 4.250 MHz (foB) 3.5795 MHz 3.5756 MHz 3.5820 MHz 4.4336 MHz n/a n/a 000 001 010 011 100 101 110 111
Standard Code
Note 1: Codes 110 and 111 are associated with "No Standard".
From this list of possible standards, the user must complete the Automatic Standard Recognition table required for the automatic search. Identification will be restricted to the table entries and the first entry will be tried first. Entering code 110 or 111 in the Automatic Standard Recognition table terminates the standard sequence search. It is possible to enter several times the same code. The Automatic Standard Recognition table and its default values are presented in Table 7.
Table 7: Automatic Standard Recognition Table Standard Entries
Standard 1 Standard 2 Standard 3 Standard 4 Standard 5 Standard 6 Standard 7 Standard 8 000 001 010 111 001 001 111 111
Code (Default values)
Register
DDECCONT4[5:0]
DDECCONT3[5:0]
DDECCONT2[5:0]
DDECCONT1[5:0]
If the default values are used, code 111 (no standard) is the fourth entry and the standard identification will be restricted to the first three standards (in order PAL BGDHI, SECAM and NTSC M). Each standard recognition trial period lasts 2 fields. All trials corresponding to table entries are performed. The identification decision is based on the results of the trials and a single table entry
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Functional Description
STV2310
should be identified. If two entries are identified by error, the standard recognition sequence will restart from the beginning of the table and no standard will be identified. The DDECCONT4[5:0], DDECCONT3[5:0], DDECCONT2[5:0], and DDECCONT1[5:0] registers are used to program the Automatic Standard Recognition table. After the sequence search, a second step (also called a confirmation step) is performed by the algorithm. It is performed on the single identified Automatic Standard Recognition table entry. It is possible to program the number of fields where the standard identification must be confirmed before the status flags are modified. The confirmation code is described in Table 8.
Table 8: Confirmation Codes Confirmation Code
000 001 010 011 1 3 (Default) 7 10
Number of Successive Fields with Correct Identification
The confirmation code is programmed in the STI_NB_FIELDS_CONFIRM[2:0] bits of the DDECCONT17 register. After the confirmation step has been successful, the standard is considered as identified. The TVSTID flag is set in the DDECSTAT2 register and the code of the identified standard is set in the TVSTD[2:0] bits of the DDECSTAT2 register.
4.6
Standard Identification
The input signal standard is automatically recognized using a proprietary ST patented algorithm. It avoids false identification and ensures a good recognition of the color standard, even in bad signal conditions.
4.7
4.7.1
Chroma Demodulation
General Description
The Chroma PLL and the Input SRC are the main hardware blocks involved in chroma demodulation. The Chroma PLL is locked to the input video burst signal in frequency and phase. Demodulation is performed on the chroma samples positioned in the virtual 4 x fSC clock domain. Dedicated demodulation hardware is used for SECAM demodulation (frequency modulated signals). Demodulated chroma components are low pass filtered and matrixed into Cr and Cb components. The Chroma Demodulator also includes an Automatic Chroma Control (ACC) which rescales the chroma components from -20 dB to +6 dB. The color is killed (output Cr Cb components to 80h value) until the standard is identified. ACC is disabled (fixed gain) in SECAM standard. If NTSC M or NTSC 4.43 standards are identified, the Chroma Demodulator also incorporates a Hue Control mechanism and a Flesh Tone Correction mechanism. The Hue Control is a programmable fixed offset in the demodulation angle and is only operational in the active line.
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STV2310
Functional Description
The Flesh Tone Correction mechanism operates with a programmable reference axis. It performs an on-the-fly change of demodulation axis for any color with a phase of approximately 39.4 around the reference axis. It is only operational in the active video line. Flesh Tone Correction (c) is up to a maximum of 10. Cr and Cb amplitudes can be adjusted separately. (See Section 4.12.1 .)
4.7.2
Programming
For NTSC standards, there are several ways to improve the video input. The hue value is controlled by the HUECTRL[5:0] bits in the DDECCONT2 register. The hue control value is defined in 63 steps of approximately 1.4 degrees each, which provide an offset between -45.0 and +43.6. When 00000, the hue angle is 0, otherwise the value of the hue angle is coded in 2's complement. An Automatic Flesh Control is also available with the STV2310. This mode is enabled by setting the FLESH_EN bit in the DDECCONT10 register. For the Automatic Flesh Control Phase Shift selection, the Flesh Tone Reference Angle in the [B-Y, R-Y] axis system is either 123 or 117. This value is selected in the FLESHPH_SEL bit of the DDECCONT10 register. The Color Kil control mode can be automatic, depending on the standard identification, or forced On or Off by the DEM_CKILL_CTRL[1:0] bits in the DDECCONTD register. In PAL/NTSC mode, it can also depend on burst amplitude by setting the in the DDECCONTF register. A pedestal can be removed from the luminance input signal by the video standard using the PEDESTAL_REMOVE bit in the DDECCONT2 register.
Figure 13: Phase Correction when Automatic Flesh Control Enabled
Phase Correction (c) +10 0 0 - 29.5 0 - 39.4 -10
0 = 123 or 117 0 + 39.4 Input Subcarrier Phase (degrees)
0 + 29.5
4.8
4.8.1
Soft Mixer
General Description
The Soft Mixer is used to mix the Y, Cr and Cb data flows (respectively) from the CVBS source and the RGB Insertion block. The mixing of the data flows is controlled by Fast Blanking mode. A forced CVBS or RGB flow mode can also be programmed. In this case, the mixer acts as a multiplexer. A static mixing (also called alpha blending) mode is also programmable. When the normal mixing mode is programmed, the CVBS and RGB flows are blending according to the Fast Blanking (FB) signal. The FB signal is sampled with subpixel accuracy to ensure correct mixing. The mixing slope between flows is programmable.
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Functional Description 4.8.2 Programming
STV2310
Fast Blanking mode is selected by the FBLANKMODE[2:0] bits in the DDECCONT5 register.
Table 9: Fast Blanking Modes Bit Value
00x 01x 100
Mixing Mode
Normal Mixing mode Dynamic Mixer mode Static Mixer or Alpha Blending 1 mode Static Mixer or Alpha Blending 2 mode Forced CVBS mode Forced RGB mode
Description
FB active during active line. Soft Mixing between 0 and 1. (Default mode) FB active and Soft Mixing from 0 to MIXSLOPE[7:0] FB inactive. YOUT = alpha x YCVBS + (1-alpha) x YRGB with alpha = MIXSLOPE[7:0] (same for Cr and Cb signals) FB inactive. YOUT = alpha x YRGB + (1- alpha) x YCVBS with alpha = MIXSLOPE[7:0] (same for Cr and Cb signals) FB inactive. YOUT = YCVBS (same for Cr and Cb signals) FB inactive. YOUT = YRGB (same for Cr and Cb signals)
101
110 111
Note:
The FBLANKMODE value is only applied when the STV2310 is not in Analog YCrCb mode The soft mixing slope or the Alpha Blending value, depending on the Fast Blanking mode, is set in the MIX_SLOPE[7:0] bits in the DDECCONT6 register. When the blanking mode is in Forced RGB or Forced CVBS mode, this value is ignored. When one of the Alpha Blending modes is used for mixing, the alpha value is set in the MIX_SLOPE[7:0] bits. When the STV2310 is in normal RGB and CVBS mixing mode, the MIX_SLOPE[3:0] bits indicate the mixing slope (duration of mixing). The MIX_SLOPE[7:4] bits must be set to 0000. The MIX_SLOPE[3:0] bits code the soft mixing slope from 0000 to 1111, with 0000 corresponding to a slope of 1 clock cycle (virtual 4 x fSC clock domain) and 1111 corresponding to a transition from one signal to the other spanned on 16 clock cycles.
4.9
4.9.1
Output Scaler and Format Converter
General Description
An Output Sample Rate Converter (OSRC) is used to transpose the subcarrier locked virtual clock domain to the output sample rate domain. This converter is used to provide a fixed number of pixels per active line (i.e. 720 for ITU-R BT.601 format) independently of the input video standard and line length.

Upsampling is required for zoom-in functions. Downsampling is required for zoom-out functions.
The Output Sample Rate Converter compensates for line length variations. At this level, a skew correction is applied on each pixel in order to compensate for the shift of the asynchronous acquisition with respect to the current line horizontal sync pulse. New sample rate and skew correction factors are computed at every line, taking into account the line length variation. The Output Sample Rate Converter is also used to perform an horizontal format conversion to support zoom in/out functions. For linear scaling, the scaling factor can be programmed in linear steps from 0.25 to 4. Non-linear scaling is also available for Panorama mode. Region borders are fully programmable as well as the associated scaling factors (in the 0.25 to 4 range).
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STV2310
Functional Description
At the sample rate converter output, an active line is transposed into a fixed number of skew corrected pixels, according to the selected output format (ITU-R BT.601 or square pixel). This is used for the orthogonal display or field storage for the field-rate up-conversion, using an external up-converter. 4.9.1.1 Square Pixel Mode When a standard TV screen is used to display computer-generated images, Square Pixel mode is required to ensure the correct aspect ratio in relation to the required sampling frequency of the TV display format.
Table 10: TV Display Formats Luma Sampling Frequency
13.5 MHz 12.27 MHz 14.75 MHz
Format
ITU-R BT.601 (NTSC/PAL) NTSC Square Pixel PAL Square Pixel
Pixels/Line
720 640 768
The output formatting can be performed with Normal or Square Pixel modes. For Square Pixel mode, the number of required samples per line depends on the input standard.
Table 11: Required Samples per Line for Square Pixel Mode Samples per Line Standard Y SIgnal
625 Lines/50 Hz 525 Lines/60 Hz 768 640 384 320
Cr Signal
384 320
Cb Signal
4.9.1.2 Zoom-In Mode In Zoom-In mode, a portion of the TV scan line is expanded to take all the available output samples for that line.The zoom-in factor ranges from 1 (no zoom) to 4 (large zoom). The Zoom-In mode start position is programmable.
Figure 14: Zoom-In Mode Programmable Offset Input Line
Output Line after zoom 720 Samples (Y Normal Pixel Mode) 2 Examples for Zoom In Action
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Functional Description
4.9.1.3 Zoom-Out Mode
STV2310
In Zoom-Out mode, the entire input TV scan line is compressed to take only a part of the output line. The active samples are positionned in the center of the output line and the rest of the line is blacked out. The zoom-out factor ranges from 0.25 (large zoom) to 1 (no zoom).
Figure 15: Zoom-Out Mode
Input Line
Output Line after zoom
Black Level
Black Level
720 Samples (Y Normal Pixel Mode)
4.9.1.4 Panorama Mode (Non-Linear Scaling) To better display wider TV screen aspect ratios, Panorama mode applies a different zoom factor to the center of the image in relation to the edges; i.e. a Non-Linear Scaling mode must be implemented. This implies that the compression/expansion factor will vary on the edges and remain stable at the center. Note in Figure 16 that the resulting TV image is symetrical (right and left edges are equal).
Figure 16: Non-Linear Scaling Zoom Factor Zoom-Out
Left Edge
Center
Right Edge
Zoom-In
1
Horizontal Axis
4.9.2
Programming
4.9.2.1 Square Pixel Mode Square Pixel mode is enabled by setting the PIXMODE bit in the DDECCONT0 register. 4.9.2.2 Zoom-In Mode To enable Zoom-In mode, the ZOOMIN_EN bit in the DDECCONTB register must be set. The zoom-in value must be between 256 and 1023. A value of 512 will zoom-in the picture by a factor of 2.0; i.e. pixels are twice as large. The zoom-in factor is programmed in the ZOOMIN_FACT[9:0] bits in the DDECCONT6 and DDECCONTB registers. The default value is 256 (No Zoom).
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STV2310
Functional Description
The position where the zoom-in operation starts is programmed in the ZOOMIN_OFFSET[9:0] bits in the DDECCONTA and DDECCONTB registers. If the value is 0, the zoom-in starts at the beginning of the TV scan line (first left pixel). The number of pixels per line is based on the vertical frequency and the pixel mode. For more information, refer to Table 10. The default value is 0; i.e. the first left pixel of the active line is the first pixel of zoom. 4.9.2.3 Zoom-Out Mode To enable Zoom-Out mode, the ZOOMOUT_EN bit in the DDECCONTB register must be set. The zoom-out value must be between 256 and 1023. A value of 512 will zoom-out the picture by a factor of 0.5; i.e. pixels are twice as small. The zoom-out factor is programmed in the ZOOMOUT_FACT[9:0] bits in the DDECCONT9 and DDECCONTB registers. 4.9.2.4 Panorama Mode Panorama mode is enabled when both the ZOOMIN_EN bit in the DDECCONTB register and the ZOOMOUT_EN bit in the DDECCONTB register are set to 1. In Panorama mode, the ZOOMIN_FACT, the ZOOMOUT_FACT and the ZOOMIN_OFFSET values are used (see Figure 16).

The ZOOMIN_FACT bits determine the zoom-in factor at the left and right edges of the picture The ZOOMOUT_FACT bits determine the zoom-out factor at the center of the picture The ZOOMIN_OFFSET bits determine the border width where the zoom factor increases from the zoom-in factor to the zoom-out factor, starting from the left edge (resp. the border width finishing on the right edge where the zoom factor decreases from the zoom-out factor to the zoom-in factor)
For correct programming the following formula must be checked: Zt x (Zout - Zin) = N x (Zout -1) where Zin = ZOOMIN_FACT ; Zout = ZOOMOUT_FACT ; Zt = ZOOMIN_OFFSET ; N number of Y pixels per line (720 in Normal Pixel mode, 640 or 768 in Square Pixel mode).
4.10
RGB Insertion
4.10.1 General Description
The RGB signals are captured by three 8-bit A/D converters and should be synchronous to the selected CVBS or Y/C sources. The RGB signals are also adjusted in the analog domain by clamp circuits used for sourcing and sinking charges on the front end capacitor. A digital adjustable gain can be applied to the RGB data flow, in order to adapt to the CVBS dynamic range. The RGB signals are YCrCb formatted and mixed with the YCrCb signals from the main picture. Soft mixing is driven by the FB signal. The rising and falling edges of the FB signal are measured with subpixel accuracy to perform correct insertion. (For more information, refer to Section 4.8: Soft Mixer on page 23). The RGB insertion block also provides a Cr Cb overload mechanism. This mechanism is used to avoid clipping YCrCb signals (i.e when the input RGB signals are too large). The Cr Cb overload
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Functional Description
STV2310
mechanism measures the chroma signal during the video line in order to compute the correcting scale factor.
Figure 17: RGB Capture and Mixing with Main Picture
R Clamp G Clamp B Clamp
Main Picture (YCrCb)
R G B
8-bit A/D Converter
Y Conversion Cr Matrix Cb 4:2:2 Formatting and Processing Soft Mixer Y Cr Cb
FB
6-bit Interpolator
4.10.2 Programming
To enable the CrCb overload mechanism, set the CRCBOVER_EN bit in the DDECCONTB register. The automatic gain for the RGB is set in the DDECCONT35 register.
4.11
Analog YCrCb Mode
4.11.1 General Description
The STV2310 can be programmed in Analog YCrCb mode. This mode has specific input connections:

the Y analog input signal must be connected to the CVBS1_Y (or CVBS2_Y) pin the Cr and Cb analog input signals must be connected to the R_CR and B_CB input pins (respectively).
A 20 degree Tint Control mechanism is available to compensate for incorrect hue levels on the input signals. When the Analog YCrCb mode is programmed, the various clamp circuits are modified accordingly. Note: The Fast Blanking (FB) signal is not relevant in Analog YCrCb mode. This mode is a full-page display mode.
4.11.2 Programming
The YCrCb Tint Angle Correction values are programmed in the TINTANGLE[4:0] bits in the DDECCONT12 register. The tint angle is coded from -20 to +20 in steps of 1.33. These bits are coded in 2's complement. The default value is 0 (no correction).
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STV2310
Functional Description
4.12
Output FIFO and Line-locked Ouput Pixel Clock Generator
4.12.1 General Description
The Output FIFO and Line-Locked Output Pixel Clock Generator block has two functions: 1 Handle the active line data received from the Output Scaler and Format Converter and the ancillary data from the VBI slicer. The active video line data is provided on 3 buses: Y, Cr and Cb. The output flow is on 8 bit and multiplexes the Y, Cr and Cb flows. Before being multiplexed, a programmable attenuation can be applied to the Cr, Cb data. For every output line, digital preambles for synchronization and ancillary data (when available) are inserted in the output flow in compliance with standard ITUR BT 656. 2 Generate the Output Pixel Clock and associated signals. A line-locked output pixel clock is generated. This output clock is a multiple of the input line frequency. There are 4 possible multiples:

1716 or 1728 in Normal Pixel mode, 1560 or 1888 in Square Pixel mode. When there is no input signal, the output data can be blanked in option. When required the STV2310 is able to enlarge the vertical blanking area. On the other hand it is possible to disable the blanking mode during the VBI, using the "pass through" mode. (The "pass through" mode must not be selected when the TXT VBI slice is used).
4.12.2 Output Data
There are 4 data output standards which are a combination of 525/625 input standards and Normal/ Square pixel format. There are four possible multiples:

1716 or 1728 in Normal Pixel mode, 1560 or 1888 in Square Pixel mode.
For each output standard, the blanking code (Cb = 80h, Y = 10h, Cr = 80h, Y = 10h...) is used in the active line section during the Vertical Blanking Interval (VBI). (See Figure 18.)
Table 12: Frame Output Standards Output Standard 1
Input Standard Pixel Format Blanking (bytes) Active Video (bytes) Vertical Blanking Interval1 Vsync SIgnal Hsync Signal Field Signal 525/60 Hz Normal 268 + 8 1440 Lines 1 to 19 Lines 264 to 282
Output Standard 2
625/50 Hz Normal 280 + 8 1440 Lines 1 to 22 Lines 311 to 335 Lines 624 and 625
Output Standard 3
625/50 Hz Square 344 + 8 1536 Lines 1 to 22 Lines 311 to 335 Lines 624 and 625
Output Standard 4
525/60 Hz Square 272 + 8 1280 Lines 1 to 19 Lines 264 to 282
Synchronized with the output pixel clock. See below. Synchronized with the output pixel clock. Synchronized with the Hsync signal output pixel clock.
1. Lines are numbered in compliance with specification ITU-R BT470.
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Functional Description
4.12.2.1 Vsync Output Pin Modes
Figure 18: Frame Output Standards
STV2310
525 Line / 60 Hz Modes
Field (F) line 3 line 4
625 Line / 50 Hz Modes
Field F
Output Standard 1
1716 bytes line 525 line 1 (V = 1) line 19 line 20
Output Standard 2
1728 bytes (V = 1) line 22 line 23
line 625 line 1
Blanking
Field 1 (F = 0) Odd
Blanking
Field 1 (F = 0) Odd
Field 1 Active Video
(V = 0)
Field 1 Active Video
Normal Pixel Modes
(V = 0)
line 265 line 266
line 263 line 264
line 312 line 313
Blanking
Field 2 (F = 1) Even
(V = 1) line 282 line 283
Blanking
line 310 line 311 (V = 1) line 335 line 336
Field 2 (F = 1) Even
Field 2 Active Video
(V = 0)
Field 2 Active Video
(V = 0)
line 3 line 4
line 525 (V = 0) line 1
line 625 line 1
line 623 line 624 (V = 1) Blanking H = 0 SAV H = 1 EAV
H = 0 SAV H = 1 EAV
Field (F) line 3 line 4
Output Standard 4
1560 bytes line 525 line 1 (V = 1) line 19 line 20
Field F line 625 line 1
Output Standard 3
1888 bytes (V = 1) line 22 line 23
Blanking
Field 1 (F = 0) Odd
Blanking
Field 1 (F = 0) Odd
Field 1 Active Video
Field 1 Active Video
Square Pixel Modes
(V = 0)
(V = 0)
line 265 line 266
line 263 line 264
line 312 line 313
Blanking
Field 2 (F = 1) Even
(V = 1) line 282 line 283 Field 2 (F = 1) (V = 0) Even
Blanking
line 310 line 311 (V = 1) line 335 line 336
Field 2 Active Video
Field 2 Active Video
(V = 0)
line 3 line 4
line 525 (V = 0) line 1
line 625 line 1
line 623 line 624 (V = 1) Blanking H = 0 SAV H = 1 EAV
H = 0 SAV H = 1 EAV
4.12.2.2
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STV2310
Functional Description
For all output standards, the Vsync output signal changes twice per frame. The Vsync signal (pin 34) can be generated at the output in one of two modes: 1 "Digital" Vsync mode: The VSYNC signal always changes at the beginning of the line, depending on the output standard. 2 "Analog" Vsync mode: The VSYNC signal changes either at the beginning or the middle of the line, depending on the analog input signal.
for Output Standard 1: Start of line 4 and middle of line 266 for Output Standard 2: Start of line 1 and middle of line 313 for Output Standard 3: Start of line 1 and middle of line 313 (same as standard 2) for Output Standard 4: Start of line 4 and middle of line 266
Note that the output standard depends on the input TV standard and the programmable Normal Pixel or Square Pixel mode. The VSYNC output mode is selected by the VSYNCTYPE bit in the DDECCONT0 register. The V bit of the output flow always changes at the beginning of the line (in compliance with standard ITU-R BT 656). Non-Interlaced mode: When required, the STV2310 is able to interlace the output, even if the source is non-interlaced (by default, the output Vsync follows the input Vsync). 4.12.2.3 Hsync Output Pin Mode The Hsync output pulse can shifted, this is in comparision with the embedded Hsync pulse. 4.12.2.4 FIELD Output Pin Mode The FIELD output pulse represents the parity of the field and toggles either with the embedded FIELD pulse, or is synchronous with the Vsync pin, when set in analog interlaced mode. To toggle in analog interlaced mode, the direct parity mode must be selected.
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Functional Description
4.12.2.5 Output Standard 1 : Normal Pixel mode / 525 lines / 60 Hz (NTSC) EAV code F0 F0 4
Xand Y are computed as checksums
STV2310
Description of Different Sections of Output Standard 1 description of EAV code on 4 bytes
0
X
0Y
SAV code F F 0 4 blanking code on 268 bytes 8 0 1 0 8 0 1 --- repeated pattern 0 8 0 1 0 81 0 0 1 0 0 X Y description of SAV code on 4 bytes
00
--- repeated pattern
268 bytes co-sited co-sited co-sited
Cb Y Cr Y Cb Y Cr Y 1440 bytes
Cb Y Cr Y
Overview of output video line and corresponding H signal EAV code Blanking SAV code Active Video line
1716 bytes
H
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STV2310
Functional Description
Digital Output Frame Overview for Output Standard 1 1716 bytes line 4 Blanking Blanking code (80 10) also in active line section Field 1 (F=0) Odd Field 1 Active Video Active video in active line section line 20 (V=0) line 1 V=1
line 266 Blanking
line 264 (V=1) Blanking code (80 10) also in active line section line 283 (V=0)
Field 2 (F=1) Even
Field 2 Active Video Active video in active line section
line 3 H=0 SAV H=1 EAV
line 525 (V=0)
Note that the vertical blanking interval has been extended from line 1 to line 19 included (transition from Field 2 to Field 1 of next Frame) and from line 264 to line 282 included (transition from Field 1 to Field 2) This encompasses the optional blanking lines described in the standard (lines 11 to 19 included and lines 273 to 282 included respectively)
The V and H signals change synchronously with the output pixel clock. The F signal change synchronously with the H signal and the output pixel clock. The V signal changes twice during one frame: - either at the start of line 1 and at the start of line 264 ("digital Vsync mode") - or at the start of line 1 and in the middle of line 263 ("analog Vsync mode")
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Functional Description
4.12.2.6 Output Standard 2: Normal Pixel / 625 lines / 50 Hz (PAL & SECAM)
EAV code F F 0 0 4 SAV code F F 0 0 4 blanking code on 280 bytes 8 0 1 0 8 0 1 --- repeated pattern 0 8 0 1 0 8 0 1 0 0 0 X Y description of SAV code on 4 bytes 0 0 X Y Description of Different Sections of Output Standard 2 description of EAV code on 4 bytes
STV2310
--- repeated pattern
1 0
280 bytes co-sited co-sited co-sited
Cb Y
Cr Y Cb Y
Cr Y 1440 bytes
Cb Y
Cr Y
Overview of output video line and corresponding H signal EAV code Blanking SAV code Active Video line
H = c9oll_h 1728 bytes
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STV2310
Functional Description
Digital Output Frame Overview for Output Standard 2 1728 bytes line 1 Blanking Blanking code (80 10) also in active line section Field 1 (F=0) Odd Field 1 Active Video Active video in active line section line 23 (V=0) line 1 V=1
line 313 Blanking
line 311 (V=1) Blanking code (80 10) also in active line section line 336 (V=0)
Field 2 (F=1) Even
Field 2 Active Video Active video in active line section
line 624 (V=1) line 625 Blanking H=0 SAV H=1 EAV line 625 (V=1)
Note that the vertical blanking interval has been extended from line 1 to line 22 included (transition from Field 2 to Field 1 of next Frame) and from line 311 to line 335 included (transition from Field 1 to Field 2)
The V and H signals change synchronously with the output pixel clock. The F signal is given as an indication. It is not output
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Functional Description
4.12.2.7 Output Standard 3: square pixel / 625 lines / 50Hz (PAL SECAM)
EAV code F F 0 0 4 SAV code F F 0 0 4 blanking code on 344 bytes 8 0 1 0 8 0 1 --- repeated pattern 0 8 0 1 0 8 0 1 0 0 0 X Y description of SAV code on 4 bytes 0 0 X Y Description of Different Sections of Output Standard 3 description of EAV code on 4 bytes
STV2310
--- repeated pattern
1 0
344 bytes (difference with normal pixel mode)
co-sited
co-sited
co-sited
Cb Y
Cr Y Cb Y
Cr Y 1536 bytes (difference with normal pixel mode)
Cb Y
Cr Y
Overview of Output Video Line and Corresponding H Signal EAV code Blanking SAV code Active Video line
H = c9oll_h
1888 bytes (difference with normal pixel mode)
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STV2310
Functional Description
Digital Output Frame Overview for Output Standard 3 1888 bytes line 1 Blanking Blanking code (80 10) also in active line section Field 1 (F=0) Odd Field 1 Active Video Active video in active line section line 23 (V=0) line 1 V=1
line 313
line 311 (V=1) Blanking Blanking code (80 10) also in active line section line 336 (V=0)
Field 2 (F=1) Even
Field 2 Active Video Active video in active line section
line 625 Blanking H=0 SAV H=1 EAV
line 624 (V=1) line 625 (V=1)
Note that the vertical blanking interval has been extended from line 1 to line 22 included (transition from Field 2 to Field 1 of next Frame) and from line 311 to line 335 included (transition from Field 1 to Field 2)
The V and H signals change synchronously with the output pixel clock. The F signal is given as an indication. It is not output
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Functional Description
4.12.2.8 Output Standard 4: Square Pixel / 525 lines / 60Hz (NTSC)
EAV code F F 0 0 4 SAV code F F 0 0 4 blanking code on 272 bytes 8 0 1 0 8 0 1 --- repeated pattern 0 8 0 1 0 8 0 1 0 0 0 X Y description of SAV code on 4 bytes 0 0 X Y Description of Different Sections of Output Standard 4 description of EAV code on 4 bytes
STV2310
--- repeated pattern
1 0
272 bytes (difference with normal pixel mode) co-sited co-sited co-sited
Cb Y
Cr Y Cb Y
Cr Y 1280 bytes (difference with normal pixel mode)
Cb Y
Cr Y
Overview of Output Video Line and Corresponding H Signal EAV code Blanking SAV code Active Video line
H = c9oll_h 1560 bytes
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STV2310
Functional Description
Digital Output Frame Overview for Output Standard 4 1560 bytes line 4 Blanking Blanking code (80 10) also in active line section Field 1 (F=0) Odd Field 1 Active Video Active video in active line section line 20 (V=0) line 1 V=1
line 266 Blanking
line 264 (V=1) Blanking code (80 10) also in active line section line 283 (V=0)
Field 2 (F=1) Even
Field 2 Active Video Active video in active line section
line 3
line 525 (V=0)
H=0 SAV H=1 EAV
Note that the vertical blanking interval has been extended from line 1 to line 19 included (transition from Field 2 to Field 1 of next Frame) and from line 264 to line 282 included (transition from Field 1 to Field 2) This encompasses the optional blanking lines described in the standard (lines 11 to 19 included and lines 273 to 282 included respectively)
The V and H signals change synchronously with the output pixel clock. The F signal is given as an indication. It is not output
4.12.3 Insertion of Ancillary Data
Ancillary data is inserted in the output flow as it is received from the VBI slicer. No operation/ modification is performed on this data. No fixed prefix or suffix is added.
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Functional Description
The ancillary data is always inserted between the EAV and SAV codes of each line.
STV2310
The line number is provided by the VBI slicer.VBI data is inserted on the next possible output line. The only lines where insertion cannot take place are the forbidden lines. The list of forbidden lines depend on the standard:

for the 525 lines (60 Hz): 9,10,11,272,273,274 for the 625 lines (50 Hz): 5,6,7,318,319,320
Ancillary data is inserted starting just after the EAV code. Ancillary data will replace the blanking data codes. Ancillary data is inserted in the same order as it is received from the VBI slicer. VBI data belonging to the same line at reception is inserted in a single line.The maximum number of ancillary data bytes to be inserted is 84.
4.12.4 Line-Locked Output Pixel Clock Generation
A phase-locked loop (PLL) generates a clock signal (CLK_DATA) that is used to read the output FIFO and to output the YCrCb data in synchronization. This output pixel clock frequency is a multiple of the input line frequency. Its value (1716, 1728, 1560 or 1888) depends on the input TV standard and the programmable Normal Pixel or Square Pixel mode. Note that phase jumps detected in the input video are replicated in the output PLL. This is equivalent to a temporary change of the number of samples per line, but no change in the output clock frequency. This feature can be disabled. In this case, the output PLL then corrects the input phase step by frequency modulation.
4.12.5 Alternate Functions: Bus Extensions
Output data is issued synchronously to the CLK_DATA clock active edge. Either the rising or falling edge of the CLK_DATA signal can be programmed as the active edge. The following pins can be used for bus extension purposes as programmable output pins: PLLLOCK, HSYNC, VSYNC and FIELD. PLLLOCK has a second alternate function IRQ (Interrrupt Request). Interrupt can be generated by several functions described in registers DDECCONT36 and DDECCONT3C.
4.12.6 Output Code Clipping
To allow compatibility with other devices, output codes can be clipped to remain inside 0 to 100% of luminance (16 to 235) and chrominance (16 to 240) components.
4.12.7 Programming
The Vsync Insertion mode for the output flow is selected in the VSYNCTYPE bit in the DDECCONT0 register. The PHSHFT_DIS bit in the DDECCONT5 register is used to disable the phase jump mechanism in the output PLL. By default, phase jumps are allowed when a phase shift in the video input is transmitted in the data flow to the output PLL. The active edge for the CLK_DATA signal is selected by the ACTEDGE bit in the DDECCONT0 register. Data is output from the STV2310 on the FIELD, VSYNC, HSYNC, PLLLOCK and YCRCB[7:0] pins which are synchronous to the CLK_DATA output clock on either the rising or falling edge (depending on the selected option). To force the Interlaced output mode, use the NONINTERLACED_EN bit in the DDECCONT18 register.
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STV2310
Functional Description
To force the pass through mode, use the PASSTHROUGH_EN bit in the DDECCONT38 register. To shift the external Hsync pulse, use the HSYNCSHIFT_DEL[1:0] and HSYNCSHIFT_EN bits in the DDECCONT22 register. Cr Cb attenuation are controlled by the DDECCONT37 and the DDECCONT38 registers. The output blanking modes are controlled by the OUTBEHAV_BLANK2 and OUTBEHAV_BLANK1 bits in the DDECCONT38 register. Output clipping is controlled by the DDECCONT18 register bit [2]. The PLLLOCK, HSYNC, VSYNC and FIELD pins may have bus extension functions. This is done by programming the OUTBUS [7:0] bits in the DDECCONT7 register.
Table 13: Output PLL Alternate Functions Bitfield
OUTBUS[0] OUTBUS[6] OUTBUS[4] OUTBUS[2]
Description
0: Standard function. 1: PLLLOCK = OUTBUS[1] 0: Standard function. 1: FIELD = OUTBUS[7] 0: Standard function. 1: VSYNC = OUTBUS[5] 0: Standard function. 1: HSYNC = OUTBUS[3]
The PLLLOCK pin has a second alternate IRQ (Interrupt Request) function, selected by the PLLLOCKIT_EN bit in the DDECCONT35 register. Note: By default, the PLLLOCK, HSYNC, VSYNC, and FIELD pins are used for their primary functions.
4.13
VBI Data Slicing and Insertion
The following standards are supported by the VBI Data Slicer (see Table 14). After slicing, VBI data is embedded in the output stream, using the intervals between the End of Active Video (EAV) and the Start of Active Video (SAV) codes of each line and formatted according to the ancillary sequences in compliance with specification ITU-R BT.656. VBI data is inserted in the Output FIFO.
Table 14: VBI Slicing Standards VBI Standards
Teletext B WST VPS WSS Closed Caption Teletext B-WST1 Closed Caption Gemstar
TV Systems (lines/freq.)
625/50 625/50 625/50 625/50 525/60 525/60 525/60
TV Lines1
6 to 22 16 23 21/22 10 to 21 21 21
Bit Rate (Mbit/s)
6.9375 2.5000 0.8333 0.5035 5.727272 0.5035 1.007
Modulation
NRZ Bi-phase Bi-phase NRZ NRZ NRZ NRZ
Bytes per Line
45 15 14 bits of data 3 37 3 5
1. Lines are numbered in compliance with specification ITU-R BT.470.
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Functional Description
Note:
STV2310
The WST - Teletext C and D (525 lines /60 Hz) formats (NATBS - MOJI) may be covered by the WST - Teletext B (525 lines -60 Hz) format.
4.13.1 VBI Formatting Features
4.13.1.1 VPS Features Video Programming System (VPS) data complies with ETSI specifications.

Search of VPS data on TV line 16 of each field Optional Extended VPS data on three TV lines (15,16 and 17) of each field Search of VPS data regardless of the field information Recognition of Start code Sampling and decoding of bytes 5 and 11 to 14 Bi-phase code check Generation of bi-phase correctness flags
4.13.1.2 WSS Features Wide Screen Signaling (WSS) data complies with ETSI specifications.

Search of WSS data on TV line 23 of each field Optional Extended WSS data on four TV lines (21, 22, 23 and 24) of each field Search of WSS data regardless of the field information Recognition of Start code Sampling and decoding of relevant 14 bits Bi-phase code check Generation of bi-phase correctness flags
4.13.1.3 WST Features World System Teletext (WST) data complies with ETSI specifications. The searched WST format is unique at a given time and is programmed by software through register-based control bits (50 Hz or 60 Hz, etc.).
Search of WST data starting at TV line 6 for 525-line broadcasts, or TV line 318 for 625-line broadcasts. Optional Extended WST data search starting at 2nd TV line (register-based control bit). Recognition and check of usual WST frame code (27h). Optional recognition and check of programmable extended frame code (register-based value but the three LSBs must be kept at `1'). Recognition of all packets or recognition of only Service Packets X/30 and X/31 (registerbased control bit). Hamming decode & check of Magazine and Page bytes for usual frame code. Split of Magazine & Page data in two separate bytes (1st byte is for Magazine, 2nd for Page).

4.13.1.4 Closed Caption Features

Search of CC data during line 21 (NTSC) or line 22 (PAL), regardless of the field information. Optional Extended slicing during all the VBI (line 5 to 25 /NTSC or 2 to 25 /PAL), regardless of the field information. Recognition and check of usual CC Frame code (11000b). Recognition and check of tighter CC Frame code (C2h).

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STV2310
Functional Description
Generation of Per-byte Parity check flags.
4.13.1.5 Gemstar Features
Search of Gemstar data during the line 21 (NTSC) or line 22 (PAL), regardless of the field information. Optional Extended slicing during all the VBI (line 5 to 25 /NTSC or 2 to 25 /PAL), regardless of the field information. Recognition and check of usual Gemstar Frame code (x011x1x1b) Recognition and check of tighter Gemstar Frame code (10110111b)

4.13.2 Data Output Format (DOF)
The Data Output Format stage will add the following data items to those received from the VBI Formatting unit:

An ancillary preamble A User Data Word Count Filler Words A User Data Word checksum Byte-to-nibble Data conversion operations Calculation of word-wise parity control bits User Data Word checksum calculation
It will then perform the following operations:

The data output flow issued by the Data Output Format is inserted into an ITU-R BT.656-type digitized stream which complies with specifications ITU-R BT.656, ITU-R BT.1364 and SMPTE 291M. In particular, the data flow follows the 8-bit data coding convention. Ancillary data is coded as "Type 2" 8-bit data items (as defined in both ITU.1364 and SMPTE 291M specifications).
EAV Blanking Interval SAV Video Digitalized Stream
A maximum of 100 bytes are used in the Blanking Interval for ancillary data. For more information, refer to Table 12: Frame Output Standards. The Data Output Format unit provides the following data on a TV line base:
The Transport layer which consists of the Ancillary Data Flag (ADF), Data ID (DID), Secondary Data ID (SDID), Data Count (DC) and Checksum Word (CS). The entire data flow generated by the Hardware Filtering, after having split each byte into nibble format. The current TV Line value, from which the data was extracted.
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Functional Description
Ancillary Data Flow For each TV line, the following sequence is generated immediately after the EAV code:
ADF
3 Bytes 00h - FFh - FFh
STV2310
DID
1 Byte 41h
SDID
1 Byte Format ID 1 Byte
DC
UDWi
User Data Words Sliced Data in nibble 1 Byte
CS
UDW Count
Checksum
DID & SDID Coding Convention All VBI data formats recognized by the Slicer use the same Data ID value. This Data ID value is programmed in the SLDID[5:0] bits in the VBICONT1 register. The default value of the DID register is "000001" respecting an 8-bit format and coding for 8-bit applications, in compliance with SMPTE 291M specifications (the full default code is 41h when parity control bits are added). Bits 6 and 7 of the DID value are hardware calculated (bit 6 is the even parity of bits 5 to 0, bit 7 is the binary complement of bit 6). Note: All possible DID values are coded using a Type 2 ancillary data coding format. The Secondary Data ID codes (SDID) identify the recognized data formats as follows:
Table 15: Secondary ID Codes SDID1
01 02 03 04 05 06 07 08 09 0A 0B 10 11 12 13
SDID Byte
41h 42h 83h 44h 85h 86h 47h 48h 89h 8Ah 4Bh 50h 91h 92h 53h VPS (No field link) Closed Caption - Field 2 Closed Caption - Field 1 Gemstar - Field 2 Gemstar - Field 1 Teletext B - 625 lines/50 Hz - Field 2 Teletext B - 625 lines/50 Hz - Field 1 Teletext B - 625 lines/50 Hz - Field 2 Teletext B - 625 lines/50 Hz - Field 1 Teletext B - 525 lines/60 Hz - Field 2 Teletext B - 525 lines/60 Hz - Field 1 Teletext B - 525 lines/60 Hz - Field 2 Teletext B - 525 lines/60 Hz - Field 1 WSS (No field link) (Not used)
Comments
Frame Code: 27h - F = 6.9375 MHz Frame Code: 27h - F = 6.9375 MHz Frame Code: XXh2 - F = 6.9375 MHz Frame Codecode: XXh2 - F = 6.9375 MHz Frame Code: 27h - F = 5.727272 MHz Frame Code: 27h - F = 5.727272 MHz Frame Code: XXh2 - F = 5.727272 MHz Frame Code: XXh2 - F = 5.727272 MHz
1. 8-bit Format 2. A different Frame Code (from the usual one) has been validated for this data. The field information can be recovered from the Data ID value.
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STV2310
Data Count (DC) Coding
Functional Description
The Data Count (DC) byte is coded according to the parity protection scheme defined in SMPTE 291M or ITU-R BT.1364 specifications, as applied to 8-bit coded data (i.e. bit 6 is the even parity check of bits 0 to 5, bit 7 is bit 6 complement to 1). In 8-bit applications, the DC byte gives a value as a 4-byte group. The number of the group of 4 User Data Words (UDW) transferred for the corresponding TV line is given in the DC byte using 6 bits. Checksum (CS) Coding The Checksum (CS) byte is coded according to the parity protection scheme defined in SMPTE 291M or ITU-R BT.1364 specifications, as applied to 8-bit coded data. Bits 6 to 0 are the LSB bits of the result of the sum of the seven LSB bits of DID, SDID, DC and all UDW bytes (any carry is dropped). Bit 7 is the complement of Bit 6. User Data Word (UDW) Coding As 00h and FFh codes are prohibited in ITU-R BT.656 specifications, each data byte is substituted by a pair of bytes; these two bytes are respectively built with:

The lower data nibble for the lower nibble of the 1st byte. The upper data nibble for the lower nibble of the 2nd byte.
Data is transmitted in the same temporal order as for the Hardware Filtering. The TV line value is also provided to the DOF block to prevent scrambling errors when the ancillary data flow is re-mixed with the video flow. User Data Word Filler As data is coded according to the 8-bit application protocol described in SMPTE 291M and ITU-R BT.1364 specifications, some extra bytes may be inserted into the User Data Word sequence. These bytes code the value 80h which is meaningless and is used only to maintain a 4-byte UDW modularity (in compliance with the above specifications). These meaningless bytes are also used to maintain the most adequate 4-byte wise data storing format handled by the microcontroller. When an application is running, it is important that these filler bytes are not processed as valid data items. UDW Coding for WST - Teletext B For World System Teletext (WST) standards, the UDW coding scheme depends on the searched frame code. When the searched frame code is the usual code (27h), the two first UDW words code the Magazine (3 bits) and the Page (5 bits) values. In this case, there is no need to perform a nibble split on these two words.When the searched frame code is validated with a programmable value, a split of the two first words is applied (as they may not be necessarily Hamming 8/4 coded). The above bytes are followed by 80 bytes (respectively 64 bytes in 525/60Hz) resulting of the nibble split of the 40 bytes (respectively 32 bytes in 525/60Hz) decoded from the current TV ancillary data.
Table 16: Magazine and Page Coding Bit
Magazine Byte Coding
7
Bit 6 1's complement
6
Even parity check for bits [5:0]
5
Always 0
4
3
2
Magazine value
1
0
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Functional Description
Table 16: Magazine and Page Coding Bit
Page Byte Coding
STV2310
7
Bit 6 1's complement
6
Even parity check for bits [5:0]
5
Always 0
4
Page value
3
2
1
0
In both cases, two filler bytes are added immediately after the last meaningful User Data Word in order to maintain a Data Count value that is a multiple of 4 bytes. All UDW bytes are coded according to the parity protection scheme defined in SMPTE 291M or ITU-R BT.1364 specifications, as applied to 8-bit coded data (i.e. bit 6 is the even parity check of bits 0 to 5 and bit 7 is bit 6 complement to1).
Table 17: UDW Coding for WST Frame Code
WST - 625 lines/50 Hz WST - 625 lines/50 Hz WST - 525 lines/60 Hz WST - 525 lines/60 Hz 27h xxh 27h xxh Byte.count Byte.count Byte.count Byte.count
ADF
3 3 3 3
DID
1 1 1 1
SDID
1 1 1 1 1 1 1 1
DC
Other MAG PAGE UDW FIL1 Bytes
1 0 1 0 1 0 1 0 80 84 64 68 1 0 1 0
FIL2
1 0 1 0 1 1 1 1
CS
Note:
"FIL1" and "FIL2" stand for Filler Bytes 1 and 2.
Table 18: UDW Byte Contents
Byt e
1
625 lines / 50 Hz Content (Framing = 27h)
Decoded Magazine value
625 lines / 50 Hz Content (Custom Framing)
LSB of Raw sliced 1st byte MSB of Raw sliced 1st byte LSB of Raw sliced 2nd byte MSB of Raw sliced 2nd byte LSB of Next raw byte MSB of Next raw byte ... ... LSB of Last raw byte MSB of Last raw byte
Byt e
1
525 lines / 60 Hz Content (Framing = 27h)
Decoded Magazine value
525 lines / 60 Hz Content (Custom Framing)
LSB of Raw sliced 1st byte MSB of Raw sliced 1st byte LSB of Raw sliced 2nd byte MSB of Raw sliced 2nd byte LSB of Next raw byte MSB of Next raw byte ... LSB of Last raw byte MSB of Last raw byte ...
2
Decoded Page value
2
Decoded Page value
3
LSB of 1st data byte MSB of 1st data byte LSB of 2nd data byte MSB of 2nd data byte ... ... LSB of 40th data byte MSB of 40th data byte
3
LSB of 1st data byte MSB of 1st data byte LSB of 2nd data byte MSB of 2nd data byte ... LSB of 32nd data byte MSB of 32nd data byte ...
4
4
5 6 ... ... 83 84
5 6 ... 67 68 ...
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STV2310
UDW Coding for VPS
Functional Description
In Video Programming Systems (VPS), a nibble split algorithm is applied. In all bytes, bit 6 is the even parity check of bits 5 to 0. Bit 7 is the complement of bit 6.
Table 19: UDW Coding for VPS
ADF DID SDID DC VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD VPUD CS 00 01 10 11 20 21 30 31 40 41 S0 S1
The result of the VPS sliced information is providing 12 bytes of data, which are generated in the following order:
VPUD00: This byte provides the LSB contents of VPS byte 5.
bit 7 6 5 0 4 0 3 RX3 2 RX2 1 RX1 0 RX0
VPUD01: This byte provides the MSB contents of VPS byte 5.
bit 7 6 5 0 4 0 3 SD1 2 SD0 1 RR1 0 RR0
SD[1:0]Sound bits RR[1:0]R-Rating bits for flagging material not suitable for children. RX[3:0]Reserved bits for future applications. Presently not defined.
VPUD10: This byte provides the LSB contents of VPS byte 11.
bit 7 6 5 0 4 0 3 ADT2 2 ADT1 1 ADT0 0 AMT3
VPUD11: This byte provides the MSB contents of VPS byte 11.
bit 7 6 5 0 4 0 3 ID1 2 ID0 1 ADT4 0 ADT3
ID[1:0]Identification of the address for this VPS line. ADT[4:0]Announced day of transmission. AMT[3]Announced month of transmission.
VPUD20: This byte provides the LSB contents of VPS byte 12.
bit 7 6 5 0 4 0 3 ASH3 2 ASH2 1 ASH1 0 ASH0
VPUD21: This byte provides the MSB contents of VPS byte 12.
bit 7 6 5 0 4 0 3 AMT2 2 AMT1 1 AMT0 0 ASH4
AMT[2:0]Announced month of transmission. ASH[4]Announced start hour.
VPUD30: This byte provides the LSB contents of VPS byte 13.
bit 7 6 5 0 4 0 3 ASM1 2 ASM0 1 NC3 0 NC2
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Functional Description
STV2310
VPUD31: This byte provides the MSB contents of VPS byte 13.
bit 7 6 5 0 4 0 3 ASM5 2 ASM4 1 ASM3 0 ASM2
ASM[5:0]Announced start minute. NC[3:0]Nationality code which is used to identify the source of the item.
VPUD40: This byte provides the LSB contents of VPS byte 14.
bit 7 6 5 0 4 0 3 PSC3 2 PSC2 1 PSC1 0 PSC0
VPUD41: This byte provides the MSB contents of VPS byte 14.
bit 7 6 5 0 4 0 3 NC1 2 NC0 1 PSC5 0 PSC4
NC[3:0]Nationality code which is used to identify the source of the item. PSC[5:0]Program source code used to identify the source of the item inside the country identified in the nationality code.
VPUDS0: This byte provides the result of data coding checks.
bit 7 6 5 0 4 0 3 VPSER4 2 VPSER3 1 VPSER2 0 VPSER1
VPUDS1: This byte provides the result of data coding checks.
bit 7 6 5 0 4 0 3 0 2 0 1 VPSVDA 0 VPSER5
VPSVDA:Valid VPS Data. This bit is set when the VPS Start code has been matched and a full VPS data flow has been sliced. When this bit is reset, it indicates that at least part of the VPS data flow has not been received (in case of a too short TV line, for example). VPSER1:Bi-phase error in the 1st VPS Byte. Data is written but there was a bi-phase error. VPSER2:Bi-phase error in the 2nd VPS Byte. Data is written but there was a bi-phase error. VPSER3:Bi-phase error in the 3rd VPS Byte. Data is written but there was a bi-phase error. VPSER4:Bi-phase error in the 4th VPS Byte. Data is written but there was a bi-phase error. VPSER5:Bi-phase error in the 5th VPS Byte. Data is written but there was a bi-phase error. UDW Coding for WSS In Wide Screen Signaling (WSS), a nibble split algorithm is applied. In all bytes, bit 6 is the even parity check of bits 5 to 0. Bit 7 is the complement of bit 6.
Table 20: UDW Coding for WSS
ADF DID SDID DC WSUD 00 WSUD 01 WSUD 10 WSUD 11 WSUD 20 WSUD 21 WSUD 30 WSUD 31 CS
WSUD00: This byte provides the LSB contents of the WSS 1st group of data.
bit 7 6 5 0 4 0 3 WSS3 2 WSS2 1 WSS1 0 WSS0
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STV2310
Functional Description
WSUD01: This byte provides the MSB contents of the WSS 1st group of data.
bit 7 6 5 0 4 0 3 0 2 0 1 0 0 WSSER1
WSSER1:WSS data group 1 error flag. This bit is set when any of the Group 1 bits (WSS[3:0]) is received with a bi-phase error. WSS[3:0]:WSS Aspect Ratio Bits.
WSUD10: This byte provides the LSB contents of the WSS 2nd group of data.
bit 7 6 5 0 4 0 3 WSS7 2 WSS6 1 WSS5 0 WSS4
WSUD11: This byte provides the MSB contents of the WSS 2nd group of data.
bit 7 6 5 0 4 0 3 0 2 0 1 0 0 WSSER2
WSSER2:WSS data group 2 error flag. This bit is set when any of the Group 2 bits (WSS[7:4]) is received with a bi-phase error. WSS[7:4]: WSS Enhanced Services Bits.
WSUD20: This byte provides the LSB contents of the WSS 3rd group of data.
bit 7 6 5 0 4 0 3 WSSER3 2 WSS10 1 WSS9 0 WSS8
WSUD21: This byte is static and provides no information.
bit 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0
WSSER3:WSS data group 3 error flag. This bit is set when any of the Group 3 bits (WSS[10:8]) is received with a bi-phase error. WSS[10:8]: WSS Subtitle Bits.
WSUD30: This byte provides the LSB contents of the WSS 4th group of data.
bit 7 6 5 0 4 0 3 WSSER4 2 WSS13 1 WSS12 0 WSS11
WSUD31: This byte provides the MSB contents of the WSS 4th group of data.
bit 7 6 5 0 4 0 3 0 2 0 1 0 0 WSSVDA
WSSVDA:Valid WSS Data. This bit is set when the WSS Start code has been matched and a full WSS data flow has been sliced. When this bit is reset, it indicates that at least part of the WSS data flow has not been received (in case of a too short TV line, for example). WSSER4:WSS Data Group 4 Error Flag. This bit is set when any of the Group 4 bits (WSS[13:11]) is received with a bi-phase error. WSS[13:11]: WSS reserved Bits.
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Functional Description
UDW Coding for CC
STV2310
In Closed Caption (CC) systems, a nibble split algorithm is applied. In all bytes, bit 6 is the even parity check of bits 5 to 0. Bit 7 is the complement of bit 6.
Table 21: UDW Coding for CC
ADF DID SDID DC CCUD 00 CCUD 01 CCUD 10 CCUD 11 CCUD L0 CCUD L1 FIL0 FIL1 CS
CCUD00: This byte provides the LSB contents of the CC 1st byte of data.
bit 7 6 5 0 4 0 3 CC3 2 CC2 1 CC1 0 CC0
CCUD01: This byte provides the MSB contents of the CC 1st byte of data.
bit 7 6 5 0 4 0 3 CC7 2 CC6 1 CC5 0 CC4
CCUD10: This byte provides the LSB contents of the CC 2nd byte of data.
bit 7 6 5 0 4 0 3 CC11 2 CC10 1 CC9 0 CC8
CCUD11: This byte provides the MSB contents of the CC 2nd byte of data.
bit 7 6 5 0 4 0 3 CC15 2 CC14 1 CC13 0 CC12
CCUDL0: This byte provides the contents of the CC bytes parity check.
bit 7 6 5 0 4 0 3 0 2 0 1 CCP1 0 CCP0
CCUDL1: This byte is static and provide no information.
bit 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0
CCP0:Closed Caption parity flag of the first byte CCP1:Closed Caption parity flag of the second byte
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STV2310
UDW Coding for Gemstar
Functional Description
In US Gemstar systems, a nibble split algorithm is applied. In all bytes, bit 6 is the even parity check of bits 5 to 0. Bit 7 is the complement of bit 6.
Table 22: UDW Coding for Gemstar
ADF DID SDID DC GMU D00 GMU D01 GMU D10 GMU D11 GMU D20 GMU D21 GMU D30 GMU GMPF GMPF FIL0 D31 L0 L1 FIL1 CS
GMUD00: This byte provides the LSB contents of the Gemstar 1st byte of data.
bit 7 6 5 0 4 0 3 GM3 2 GM2 1 GM1 0 GM0
GMUD01: This byte provides the MSB contents of the Gemstar 1st byte of data.
bit 7 6 5 0 4 0 3 GM7 2 GM6 1 GM5 0 GM4
GMUD10: This byte provides the LSB contents of the Gemstar 2nd byte of data.
bit 7 6 5 0 4 0 3 GM11 2 GM10 1 GM9 0 GM8
GMUD11: This byte provides the MSB contents of the Gemstar 2nd byte of data.
bit 7 6 5 0 4 0 3 GM15 2 GM14 1 GM13 0 GM12
GMUD20: This byte provides the LSB contents of the Gemstar 3rd byte of data.
bit 7 6 5 0 4 0 3 GM19 2 GM18 1 GM71 0 GM16
GMUD21: This byte provides the MSB contents of the Gemstar 3rd byte of data.
bit 7 6 5 0 4 0 3 GM23 2 GM22 1 GM21 0 GM20
GMUD30: This byte provides the LSB contents of the Gemstar 4th byte of data.
bit 7 6 5 0 4 0 3 GM27 2 GM26 1 GM25 0 GM24
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Functional Description
STV2310
GMUD31: This byte provides the MSB contents of the Gemstar 4th byte of data.
bit 7 6 5 0 4 0 3 GM31 2 GM30 1 GM29 0 GM28
GMUDL0: This byte provides the contents of the Gemstar bytes parity check.
bit 7 6 5 0 4 0 3 GMP3 2 GMP2 1 GMP1 0 GMP0
GMUDL1: This byte is static and provide no information.
bit 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0
GMP0: Gemstar parity flag of the first byte GMP1: Gemstar parity flag of the second byte GMP2: Gemstar parity flag of the third byte GMP3: Gemstar parity flag of the fourth byte
4.14
IC Bus Specifications
Data transfers follow the usual IC format: after the start condition (S), a 7-bit slave address is sent, followed by an eight-bit which is a data direction bit (W). An 8-bit sub-address is sent to select a register, followed by an 8-bit data word to be included in the register. The circuit operates at clock frequencies of up to 400 kHz. The IC's IC bus decoder allows the automatic incrementation mode in write mode. String Format Write Only mode (S = Start Condition, P = Stop Condition, A = Acknowledge)
S SLAVE ADDRESS 0 A REGISTER N A DATA N A P
Read Only mode
S SLAVE ADDRESS 0 A REGISTER N A P
S
SLAVE ADDRESS
1
A
DATA N
A
DATA N+1
A
P
Slave Address
Address Value A7 1 A6 0 A5 0 A4 0 A3 I2CADD A2 1 A1 1 A0 R/W
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STV2310
Table 23: Alternate IC Addresses
I2CADD = 0 Write Address Read Address 86h 87h I2CADD = 1 Write Address Read Address
Functional Description
8Eh 8Fh
For the exact numerical values of the IC timing characteristics, please refer to the IC Bus Characteristics on page 105.
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Register List
STV2310
5
Register List
This section lists the Control and Status registers for the IC interface. Registers are called as output ports and are named as follows:

DDECCONT[n][7:0] for non-VBI Control registers DDECSTAT[n][7:0] for Status registers (Read Only) VBICONT[n][7:0] for VBI Control registers
5.1
Register Map
Name
Add. Reset Value (h) (Bin)
00h 0000 0100
Register Function and Description Bit 7
VSYNC TYPE
Bit 6
PIXMODE
Bit 5
ACT EDGE
Bit 4
CVBS MUX
Bit 3
OUTTRI STATE
Bit 2
SVIDEO SEL
Bit 1
Bit 0
DDECCONT0 DDECCONT1 DDECCONT2 DDECCONT3 DDECCONT4 DDECCONT5 DDECCONT6 DDECCONT7 DDECCONT8 DDECCONT9 DDECCONTA DDECCONTB DDECCONTC DDECCONTD
5060MODE[1:0]
01h 02h
0011 1111 0100 1001
BLANKMODE[1:0] PEDESTAL _REMOVE
AUTOSTD[5:0] AUTOSTD[11:6]
03h 04h 05h
0001 0111 0000 0001 0010 0000 CRCBOVE R_EN
AUTOSTD[17:12] AUTOSTD[23:18] FBLANKMODE[2:0] YCRCB_ MODE PHSHFT_ DIS
06h 07h 08h 09h 0Ah 0Bh
0000 0001 0000 0000 1111 1111 0100 0000 0000 0000 1100 0000 ZOOMIN_FACT[1:0]
MIX_SLOPE[7:0] OUTBUS[7:0] ZOOMIN_FACT[9:2] ZOOMOUT_FACT[9:2] ZOOMIN_OFFSET[9:2] ZOOMOUT_FACT [1:0] ZOOMIN_OFFSET [1:0] ZOOMOUT ZOOMIN_ _EN EN
0Ch 0Dh
0000 0000 0011 0100
SPC_CORING[1:0] STI_NB_FIELDS_FALS E [1:0]
ALL_NTSC_HUE_VALUE[5:0] STI_OK_O NCE_OR_ MORE DEM_CKILL_CTRL[1:0]
DDECCONTE DDECCONTF DDECCONT1 0 DDECCONT1 1 DDECCONT1 2
0Eh 0Fh 10h
0010 0110 0000 0000 0001 0000 DEM_CKILL_LVL[2:0] SPC_NTS SPC_NTS C_FLESH_ C_FLESH_ PH EN SYNC_SLICE_LEVEL[3:0] DEM_CKILL_LVL[4:0]
11h
1000 1000
12h
0000 0000
SPC_NTS C_GREEN _EN
TINTANGLE[4:0]
54/112
STV2310
Register List
Name
Add. Reset Value (h) (Bin)
13h 0000 0000
Register Function and Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DDECCONT1 3 DDECCONT1 4 DDECCONT1 5 DDECCONT1 6 DDECCONT1 7 DDECCONT1 8 DDECCONT1 9 DDECCONT1 A DDECCONT1 B DDECCONT1 C DDECCONT1 D DDECCONT1 E DDECCONT1 F DDECCONT2 0 DDECCONT2 1 DDECCONT2 2 DDECCONT2 3 DDECCONT2 4 DDECCONT2 5
14h
0000 0000
15h
0001 0000
DEM_YC_DELAY[3:0]
16h
0111 1010
SATLMTLN[1:0]
SATLMTPT[1:0]
SMHITH[1:0]
ACTITH[1:0]
17h
0110 0100
STI_50_60 HZ_EN
STI_NB_FIELDS_CONFIRM[2:0]
SPC_OVE SPC_ACC RLOAD_O _OFF FF COMB_MO DE[1:0]
18h
0101 1001
BW_SEL[2:0]
NONINTE RLACED_ EN
SATCODE _EN
19h
0100 0100
1Ah
0010 0000
1Bh
1000 0100
1Ch
1000 0100
1Dh
1000 1000
1Eh
1001 1001
1Fh
0001 1000
DIRECTPA RITY
20h
0000 0100
21h
0010 1011
BLKLINE[1:0]
22h
1110 1000
HTIMECST HSYNCSHIFT_DEL[1:0] HSYNCSHI SEL FT_EN
23h
1010 1010
24h
1000 0111
25h
1001 0100
HSYNC_ SAV
NOISE_THRESHOLD[2:0]
55/112
Register List
STV2310
Name
Add. Reset Value (h) (Bin)
26h 0100 0100
Register Function and Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DDECCONT2 6 DDECCONT2 7 DDECCONT2 8 DDECCONT2 9 DDECCONT2 A DDECCONT2 B DDECCONT2 C DDECCONT2 D DDECCONT2 E DDECCONT2 F DDECCONT3 0 DDECCONT3 1 DDECCONT3 2 DDECCONT3 3 DDECCONT3 4 DDECCONT3 5 DDECCONT3 6 DDECCONT3 7 DDECCONT3 8
27h
0110 0110
28h
1000 0010
HUNLOCK_LINE_NUM[3:0]
HLOCK_LINE_NUM[3:0]
29h
0101 0101
HLOCK_PH_ER_TH[3:0]
2Ah
1000 0010
CLAM_PROP[1:0]
CLAM_DER[1:0]
CLAMP_INT[2:0]
2Bh
0110 0011
2Ch
1000 0010
2Dh
0000 1010
2Eh
0000 0000
2Fh
0000 0000
OVERDRIV OVERDRIVE_SEL[1:0] E_MODE
30h
0000 0000
31h
0010 0000
AGC_DIS
CVBSAGCGAIN[5:0]
32h
0000 0000
33h
0000 0000
34h
0000 0000
35h
0000 0000
PLLLOCKI RGBADJU T_EN ST_EN PLLLOCK_ VLOCK_M HLOCK_M TVSTDID_ MASK ASK ASK MASK CB_SCALING[1:0]
RGBADJUST[5:0]
36h
1111 0000
FBDEL[3:0]
37h
1111 1111
CR_SCALING[5:0]
38h
0010 1111
CB_SCALING[5:2]
56/112
STV2310
Register List
Name
Add. Reset Value (h) (Bin)
39h 0101 0101
Register Function and Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DDECCONT3 9 DDECCONT3 A DDECCONT3 B DDECCONT3 C VBICONT1 VBICONT2 VBICONT3 VBICONT4 VBICONT5 VBICONT6 VBICONT7 VBICONT8 VBICONT9 VBICONT0A VBICONT0B VBICONT0C VBICONT0D VBICONT0E VBICONT0F VBICONT10 VBICONT11 VBICONT12 VBICONT13 VBICONT14 VBICONT15 VBICONT16 VBICONT17 VBICONT18
3Ah
0101 0101
3Bh
0011 0101
3Ch
1111 1100
VSYNCNS TRICKDET INTERDET VCRDET_ INSERDET FBDET_M TD_MASK _MASK _MASK MASK _MASK ASK SLDID[5:0] SLFIL[5:0] SLICECO MP_EN RAWFILTO WSTSLICI FF_EN NG_EN FRAMINGCODE[7:0] WSSF1ON VPS1ONLY LY_EN _EN GMVBILIN GMRELAX GMSLICIN ES _EN G_EN VPSSLICI NG_EN VPSEXTLI WSSSLICI WSSEXTLI NES NG_EN NES CCVBILIN ES CCRELAX _EN CCSLICIN G_EN WSTCUST WSTEXTLI WSTALLPA OMFRAM NES CKETS
3Dh 3Eh 3Fh
xx00 0001 xx00 0000 1000 0001
40h 41h
0010 0111 1100 0101
42h
0000 0000
43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h
0000 1101 0000 1000 0110 0011 0001 1100 0100 0110 0000 0000 0000 0000 0000 0000 1011 0011 0000 1000 0111 0001 0000 1100 0000 0000 0000 0000 0001 0101 1010 0000 EQZPRGM EQZORDE ODE RSEL VBI_EQUALCOEFF[2:0] EQZFLTMOD[4:0] WSTH[7:0] WSTH[9:8] CGESPF2 CGSEW[2:0] CGESPF1 CGNBS[1:0] CGVS[5:0] CGNBI[2:0]
53h 54h
0101 0000 0001 0010
57/112
Register List
STV2310
Name
Add. Reset Value (h) (Bin)
7Eh 0000 0000
Register Function and Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DDECCONTF E DDECCONTF F DDECSTAT1 DDECSTAT2 DDECSTAT3
INTERDET VCRDET_ INSERDET FBDET_AC PLLLOCK_ VLOCK_A _ACK ACK _ACK K ACK CK
HLOCK_A TVSTDID_ CK ACK VSYNCNS TRICKDET TD_ACK _ACK
7Fh
0000 0000
80h 81h 82h
0001 0000 READ ONLY READ ONLY VLOCK HLOCK PLLLOCK
STVDDECVERS[7:0] 5060ID TVSTDID TVSTD[2:0] TRICKMO D_DETEC TED
VSYNCLO BLANKLVL INTERLAC DVD_DET C_NSTD _SHIFT_D ED_DETE ECTED ETECTED CTED
VCR_DET INSER_DE FB_DETE ECTED TECTED CTED
DDECSTAT4 DDECSTAT5 DDECSTAT6 DDECSTAT7 DDECSTAT8
83h 84h 85h 86h
READ ONLY READ ONLY READ ONLY READ ONLY
NOISELVL[7:0] SLDID[7:0] SLFIL[7:0] VBIERR_D GEM_DET CC_DETE ETECTED ECTED CTED VPS_DET ECTED WST_DET WSS_DET OPENLOO ECTED ECTED P
5.2
Non-VBI Control Register Descriptions
DDECCONT0 Register Description
Address: 00h Reset Value (bin): 0000 0100 Bit 7 VSYNCTYP E Bit 6 PIXMODE Bit 5 ACTEDGE Bit 4 CVBSMUX Bit 3 OUTTRISTA TE Bit 2 SVIDEOSEL Bit 1 Bit 0
5060MODE[1:0]
Bit Name
VSYNCTYPE Vsync Insertion in Output Flow
Function
The VSYNC output signal is always synchronous to the output clock (CLK_DATA). It will toggle twice per frame either in Digital or Analog mode according to this option. 0: Analog mode (Interlaced): depends on the standard: for Output Standard 1: start of line 1 and middle of line 263 for Output Standard 2: start of line 1 and middle of line 313 for Output Standard 3: start of line 1 and middle of line 313 (same as Standard 2) for Output Standard 4: start of line 1 and middle of line 263 (Default) 1: Digital mode: start of line 1/624 or start of line 264/624 (Vsync at beginning of line) Note that the analog mode is now split between an "analog output as input" mode and an "analog output with forced interlaced" output mode. For more information, see bit 3 of register DDECCONT18.
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STV2310
Register List
Bit Name
PIXMODE Pixel Mode Selection
Function
In Square Pixel mode, the number of Y, Cr and Cb components depends on the standard as shown in
Table 12. The output line locked frequency (CLK_DATA) will also change according to the standard.
0: Normal Pixel mode (Default) 1: Square Pixel mode ACTEDGE Data is output from the STV2310 on the following pads: FIELD, VSYNC, HSYNC, PLLLOCK and YCRCB[7:0]. It is synchronous to the CLK_DATA output clock either on the rising or falling edge depending on this option. 0: Clock falling edge is active edge (Default) 1: Clock rising edge is active edge CVBSMUX Y/CVBS Input Selection 0: Y/CVBS1 input (Default) 1: Y/CVBS2 input OUTTRISTATE Pad Tristate Mode The pad tristate mode depends on the chip I2C address. If the I2C default chip address is chosen: 0: Output digital pads in Output mode (Default) 1: Output digital pads in Tristate mode If the I2C spare chip address is chosen: 0: Output digital pads in Tristate mode (Default) 1: Output digital pads in Output mode Note that only the following pads can be in Tristate mode: FIELD, VSYNC, HSYNC, PLLLOCK, CLK_DATA and YCRCB[7:0]. The I2C pads are never in Tristate mode. SVIDEOSEL CVSB/S-Video Selection The S-video mode notifies the STV2310 that the chroma and luma signals are already separated. 0: S-Video Input 1: CVBS Input (Default) 5060MODE[1:0] Vsync Search Mode and initial Free-running Mode These bits provide the starting point for the Vsync extraction mechanism. 50-Hz or 60-Hz input standards are expected. The options are to look exclusively for 50-Hz or 60-Hz standards (Forced 50 or 60) or to search for all standards with a priority in the search mechanism (Auto 50 or 60). 00: Auto 50: Automatic search mode starting with 50-Hz standards. (Default) 01: Forced 60: Search mode forced to 60-Hz standards only. 10: Forced 50: Search mode forced to 50-Hz standards only. 11: Auto 60: Automatic search mode starting with 60-Hz standards.
DDECCONT1
Address (hex): 01h Reset Value (bin): 0011 1111 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BLANKMODE[1:0]
AUTOSTD[5:0]
59/112
Register List
STV2310
Bit Name
BLANKMODE [1:0] Blanking Mode
Function
The blanking mode defines how the clamp mechanism will perform. The blanking code is the ADC output code used by the clamp mechanism as target In the Auto mode and depends on the vertical sync identification result (50 or 60 Hz). The blanking code is determined in the 2 other modes. 00: Auto (50 Hz = Code 256, 60 Hz = Code 244) (Default) 01: Blanking code 256 (Sync tip 43 IRE) 10: Blanking code 244 (Sync tip 40 IRE) 11: Auto (Same as 00)
AUTOSTD[5:0]
Auto Identification Table (Seventh and Eighth Standards) The STV2310 can search for one of the TV standards programmed in the Automatic Standard Identification Table (split over several registers). The Automatic Standard Identification Table has 8 entries with an order of priority for the search. Note that in the default configuration, "No Standard" is programmed in the seventh and eigth entries. 000: PAL BGDHI100: PAL N 001: SECAM 101 NTSC 4.43 010: NTSC M110 or 111: No Standard 011: PAL M
DDECCONT2
Address (hex): 02h Reset Value (bin): 0100 1001 Bit 7 Bit 6 PEDESTAL_ REMOVE Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUTOSTD[11:6]
Bit Name
Bit 7 PEDESTAL_ REMOVE Reserved: Must be set to 0. Pedestal Remove in Input signal
Function
The PEDESTAL_REMOVE bit describes the input signal (whether a pedestal is present in the input signal or not). This information is entered by the user. Gain and offset on the Y processing will be different according to that bit. The pedestal remove function is active for all 50- and 60-Hz input standards. Note that by default, it is considered that there is no pedestal in NTSC M inputs. The pedestal remove function operates both on the CVBS and RGB flows. 0: Pedestal is present in input signal. 1: Pedestal is not present in input signal. (Default)
AUTOSTD[11:6]
Auto Identification Table (Fifth and Sixth Standards) Fifth and Sixth Standards of the Automatic Standard Identification Table. See register DDECCONT1. 001 001: SECAM (Default)
60/112
STV2310 DDECCONT3
Address (hex): 03h Reset Value (bin): 0001 0111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List Register Description
Bit 0
AUTOSTD[17:12]
Bit Name
Bits[7:6] AUTOSTD[17:12] Reserved: Must be set to 0.
Function
Auto Identification Table (Third and Fourth Standards) Third and Fourth Standards of the Automatic Standard Identification Table. See register DDECCONT1. 010 111: NTSC M and No Standard (Default)
DDECCONT4
Address (hex): 04h Reset Value (bin): 0000 0001 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUTOSTD[23:18]
Bit Name
Bits[7:6] AUTOSTD[23:18] Reserved: must be set to 0.
Function
Auto Identification Table (First and Second Standards) First and Second Standards of the Automatic Standard Identification Table. See register DDECCONT1. 000 001: PAL BGDHI and SECAM (Default)
DDECCONT5
Address (hex): 05h Reset Value (bin): 0010 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3 FBLANKMODE[2:0]
Bit 2
Bit 1 YCRCB_ MODE
Bit 0 PHSHFT_DIS
SECAM_CHRTUNING[1:0]
CRCBOVER _EN
Bit Name
SECAM_CHRTU NING[1:0] Reserved: must be set to 0.
Function
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Register List
STV2310
Bit Name
CRCBOVER_EN RGB enables the CRCB overload algorithm
Function
This bit enables the RGB CrCb overload mechanism. This mechanism is used to prevent clipping on YCrCb (when the input RGB signals are too large). The CrCb overload mechanism performs chroma measurement during the video line to compute the correcting scale factor. 0: CRCB overload algorithm not active 1: CRCB overload algorithm active FBLANKMODE [2:0] Fast Blanking Mode Selection The Fast Blanking mode is only operational when the STV2310 is not in Analog YCrCb mode. It also depends on the programmed mode and the FB input value. See register DDECCONT6. 00x: Normal mixing mode between CVBS and RGB (Default) (FB active during active line; soft mixing between 0 and 1) 01x: Saturated mode (mixing mode between CVBS and RGB) (FB active and soft mixing from 0 to MIXSLOPE[7:0]) 100: Static Mixer or Alpha Blending Mode 1 (FB inactive) YOUT = alpha x YRGB + (1-alpha) x YCVBS 101: Static Mixer or Alpha Blending Mode 2 (FB inactive) YOUT = alpha x YCVBS + (1- alpha) x YRGB with alpha = MIXSLOPE[7:0] (Same relationship for Cr and Cb) 110: Forced CVBS (FB inactive) YOUT = YCVBS (idem for Cb, Cr) 111: Forced RGB (FB inactive) YOUT = YRGB (idem for Cb,Cr) YCRCB_MODE YCrCb Mode Selection When the STV2310 is in Analog YCrCb mode, Fast Blanking Mode is disabled. 0: YCrCb signals all either from CVBS or RGB. (Default) 1: YCrCb mode: Y from CVBS signal, Cr and Cb from RGB signal with priority over FB mode. PHSHFT_DIS Phase Shift Option Disabled in Output PLL This bit disables the phase jumps mechanism in the output PLL. Phase jumps are allowed when a phase shift in the video input is transmitted in the data flow to the output PLL. 0: Phase shifts are enabled. (Default) 1: Phase shifts are disabled.
DDECCONT6
Address (hex): 06h Reset Value (bin): 0000 0001 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MIX_SLOPE[7:0]
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STV2310
Register List
Bit Name
MIX_SLOPE[7:0]
Function
Soft Mixing Slope, Alpha Blending or Saturated Value This bitfield provides the soft mixing slope or the alpha blending value depending on Fast Blanking mode. When the blanking mode is in Forced RGB or Forced CVBS mode, this bitfield is irrelevant. When the blanking mode is in one of the alpha blending modes, the MIX_SLOPE[7:0] register provides the alpha value (an FF entry means full scale). When the blanking mode is in the normal mixing mode between RGB and CVBS, the MIX_SLOPE[1:0] bits indicate the mixing slope. The MIX_SLOPE[7:2] bits must be set to 000000. The MIX_SLOPE[1:0] register codes the soft mixing slope from 00 to 11 with 00 corresponding to a slope of 1 clock cycle (4 x fSC clock domain) and 11 corresponding to a slope of 4 clock cycles. The default entry is 01, corresponding to a slope of 2 clock cycles.
DDECCONT7
Address (hex): 07h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OUTBUS[7:0]
Bit Name
OUTBUS[7:2] Alternative values driven by OUTBUS
Function
The OUTBUS[7:2] bits are linked to the HSYNC, VSYNC and FIELD pad control. When OUTBUS[2] = 0: standard function on HSYNC; when = 1: HSYNC = OUTBUS[3] When OUTBUS[4] = 0: standard function on VSYNC; when = 1: VSYNC = OUTBUS[5] When OUTBUS[6] = 0: standard function on FIELD; when = 1: FIELD = OUTBUS[7] OUTBUS[1:0] Alternative values driven by OUTBUS The OUTBUS[1:0] bits are linked to the PLLLOCK pad control. When OUTBUS[0] = 0: standard function; when = 1: PLLLOCK = OUTBUS[1]
DDECCONT8
Address (hex): 08h Reset Value (bin): 1111 1111 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ZOOMIN_FACT[9:2]
Bit Name
ZOOMIN_FACT [9:2] Zoom-in Factor from 1 to 4 (MSBs)
Function
The Zoom-in factor operates from 4 to 1 (No zoom). The LSBs of this value are in the DDECCONTB register. This value must be between 256 (x4) and 1023 (x1). 3FFh: Zoom-in factor of 1 (No zoom) (Default value) 200h: Zoom-in factor of 2 100h: Zoom-in factor of 4 (Enlarged picture)
63/112
Register List DDECCONT9
Address (hex): 09h Reset Value (bin): 0100 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0
ZOOMOUT_FACT[9:2]
Bit Name
ZOOMOUT_ FACT [9:2] Zoom-out Factor from 1 to 0.25 (MSBs)
Function
The Zoom-out factor operates from 1 (no zoom) to 0.25 (large zoom). The Zoom-out factor must be between 256 (x1) and 1023 (x0.25). The LSBs of this value are in the DDECCONTB register. 3FFh: Zoom-out factor of 0.25 (Reduced picture) 100h: Zoom-out factor of 1.0 (No zoom) (Default value)
DDECCONTA
Address (hex): 0Ah Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ZOOMIN_OFFSET[9:2]
Bit Name
ZOOMIN_ OFFSET[9:2] Zoom-in Offset (Cropping) (MSBs)
Function
The Zoom-in offset determines the section of input line used for zooming in. The Zoom-in offset value must be between 0 and the maximum number of Y pixels per line. Note that the number of pixels per line will depend on the standard and the pixel mode. Note that the Zoom-out factor is coded on 10 bits in 2 registers. The Default value is 0 = first left pixel of the active line is the first pixel of zoom.
DDECCONTB
Address (hex): 0Bh Reset Value (bin): 1100 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1 ZOOMOUT_ EN
Bit 0 ZOOMIN_EN
ZOOMIN_FACT[1:0]
ZOOMOUT_FACT[1:0]
ZOOMIN_OFFSET[1:0]
Bit Name
ZOOMIN_FACT [1:0]
Function
Zoom-in Factor (LSBs). See register DDECCONT8.
64/112
STV2310
Register List
Bit Name
ZOOMOUT_FAC T [1:0] ZOOMIN_OFFSE T[1:0] ZOOMOUT_EN
Function
Zoom-out Factor (LSBs). See register DDECCONT9.
Zoom-in Offset (LSBs). See register DDECCONTA. Zoom-out Function Enable When both Zoom-in and Zoom-out functions are enabled, the STV2310 is in Panorama mode. In Panorama mode, the ZOOMIN_FACT, the ZOOMOUT_FACT and the ZOOMIN_OFFSET are used. The ZOOMIN_FACT determines the zoom-in factor at the left and right edges of the picture. The ZOOMOUT_FACT determines the zoom-out factor at the center of the picture. The ZOOMIN_OFFSET determines the border width where the zoom factor increases from the zoom-in factor to the zoom-out factor, starting from the left edge (respectively, the border width finishing on the right edge where the zoom factor decreases from the zoom-out factor to the zoom-in factor). Correct programming is left to the user without hardware check. For programming verification, the following formula must be checked: Zt x (Zout - Zin) = N x (Zout -1) where Zin = ZOOMIN_FACT; Zout = ZOOMOUT_FACT; Zt = ZOOMIN_OFFSET; N = Number of Y pixels per line (720 in Normal Pixel mode, 640 or 768 in Square Pixel mode) 0: Zoom-out function is disabled. (Default) 1: Zoom-out function is enabled.
ZOOMIN_EN
Zoom-in Function Enable 0: Zoom-in function is disabled. (Default) 1: Zoom-in function is enabled.
DDECCONTC
Address (hex): 0Ch Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPC_CORING[1:0]
ALL_NTSC_HUE_VALUE[5:0]
Bit Name
SPC_CORING [1:0] Coring Function for all standards
Function
The Coring function is operational for all standards. When activated, the demodulated color components (Cr and Cb) close to 128 are replaced by 128. 00: No action. (Default) 01: 127 to 129 rounded to 128 (dynamic range of 1 LSB) 10: 125 to 131 rounded to 128 (dynamic range of 3 LSBs) 11: 123 to 133 rounded to 128 (dynamic range of 5 LSBs)
ALL_NTSC_HUE _VALUE[5:0]
NTSC Hue Control Function The Hue Control mechanism is only operational when the NTSC or NTSC M standard has been detected (or being tried by the standard identification algorithm). The hue is a fixed offset in a demodulation angle. The offset is only operational in the active line. There are 63 steps of approximately 1.4 degrees each, allowing an offset of between -45 and +43.6. Coded in 2's complement (0 = No Hue)
65/112
Register List DDECCONTD
Address (hex): 0Dh Reset Value (bin): 0011 0100 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 STI_OK_ON CE_OR_MO RE Bit 2 Bit 1
STV2310 Register Description
Bit 0
STI_NB_FIELDS_FALSE [1:0]
DEM_CKILL_CTRL[1:0]
Bit Name
Bit 7 STI_NB_FIELDS _FALSE[1:0] Reserved: Must be set to 0.
Function
Number of Fields where Identification is lost before declaring Loss of Identification The STI_NB_FIELDS_FALSE bits are related to the standard identification algorithm. These bits are operational on all standards. They operate in the tracking phase when a standard has been recognized. They determine the number of successive fields to reach when at least one of the criteria associated with the standard is no longer met: the standard is then considered as lost. 00: 1 field10: 7 fields 01: 3 fields11: 15 fields
Bit 4 STI_OK_ONCE_ OR_MORE
Reserved. Must be set to 1. Number of trials before standard is officially recognized The STI_OK_ONCE_OR_MORE bit is related to the internal standard identification algorithm and provides some flexibility in the standard identification. This bit is operational for all standards. As previously described, up to 8 standards can be entered in the Automatic Standard Identification table. One (or more) standard can be written more than once in that table (e.g. 4 times SECAM and 4 times PAL BGDHI). The complete standard identification table is screened and tried before a decision can be made on identification (one trial per table entry, succesful or not). When a standard has been programmed more than once and when this bit is set, all trials for all entries of that standard in the Automatic Standard Identification table must be successful before the standard is declared identified. When a standard has been programmed more than once and when this bit is reset, the standard is declared identified when at least one trial was successful. (Note that the information presented here only refers to the STI_OK_ONCE_OR_MORE bit. It does not represent the entire standard identification algorithm.)
Bit 2 DEM_CKILL_ CTRL[1:0]
Reserved. Must be set to 1. Color Kill Control The Color Kill Control mode is operational for all TV standards. In Automatic mode, the color is killed until the standard is identified. 00: Automatic (Default)10: Color always killed 01: Color never killed 11: Automatic (Same as 00) with Burst Amplitude control (see DDECCONT0F)
DDECCONTE
Address (hex): 0Eh Reset Value (bin): 0010 0110 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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STV2310
Register List
Bit Name
Bits [5:0] Bit 6 Bit 7 Reserved. Must be set to 0. Reserved. Must be set to 0. Reserved. Must be set to 0.
Function
DDECCONTF
Address (hex): 0Fh Reset Value (bin): 0000 0000 Bit 7 Bit 6 DEM_CKILL_LVL[2:0] Bit 5
Register Description
Bit 4
Bit 3
Bit 2 DEM_CKILL_LVL[4:0]
Bit 1
Bit 0
Bit Name
DEM_CKILL_LVL [2:0]
Function
Reserved. Must be set to 000. Chroma Killer Hysteresis Level The chroma kill mechanism is by default in automatic mode (see ddeccontd[7:0] register). The color is killed on the output when no chroma standard is recognised. This register offers an additional killer feature when in automatic mode. The chroma is killed when the burst amplitude is under the chroma killer automatic level. The chroma is restaured when the chroma burst amplitude is above the threshold plus the programmed hysteresis. When the chroma burst amplitude < dem_ckill_lvl[4:0], the chroma is killed. When the chroma is killed and the chroma burst amplitude > dem_ckill_lvl[4:0] + dem_ckill_lvl[7:5], the chroma is no longer killed. Reserved. Must be set to 00000. Chroma Killer Automatic Threshold. See above.
DEM_CKILL_LVL [4:0]
DDECCONT10
Address (hex): 10h Reset Value (bin): 0001 0000 Bit 7 SPC_NTSC _FLESH_PH Bit 6 SPC_NTSC _FLESH_EN Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
SPC_NTSC_FLE SH_PH
Function
Automatic Flesh Control Phase Reference Selection The Flesh Tone Reference Angle in the [B-Y, R-Y] axis system is either 123 or 117. 0: Reference Phase is 117 (Default) 1: Reference Phase is 123
SPC_NTSC_FLE SH_EN
Automatic Flesh Control Mode Enable 0: Automatic Flesh Control is disabled. (Default) 1: Automatic Flesh Control is enabled. Reserved/ Must be set to 01 0000
Bits [5:0]
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Register List DDECCONT11
Address (hex): 11h Reset Value (bin): 1000 1000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0
SYNC_SLICE_LEVEL[3:0]
Bit Name
SYNC_SLICE_LE VEL[3:0] Slicing Level Value
Function
The horizontal PLL requires a slicing level . This bitfield indicates the slicing level as a fraction between the blanking and the sync tip level. The blanking level is used as the reference level for the clamp mechanism. (See also bit BLANKMODE[1:0] in register DDECCONT1). The sync tip level is computed from the input video signal by the synchronization mechanism. 0000: Slicing Level = Blank Level 1111: Slicing Level = (Blank - sync tip )/16 + sync tip
Bits[3:0]
Reserved. Must be set to 0000.
DDECCONT12
Address (hex): 12h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2 TINTANGLE[4:0]
Bit 1
Bit 0
SPC_NTSC _GREEN_E N
Bit Name
Bits[7:6] SPC_NTSC_GRE EN_EN Reserved. Must be set to 00. Green Enhancement Mode Enable
Function
The Green Enhancement mechanism is applied to the CVBS flow only and is only valid for the NTSC M and the NTSC 4.43 standards. The green tone axis has been defined as flesh tone axis + 90 degrees in the vectorscope representation (i.e. 213 or 207 degrees). Green enhancement is only performed during the active line. Green enhancement operates through saturation increase. Saturation increase factor k is a linear function of the color phase distance to green axis. k = 1 for color phase - green axis = 22.5 degrees (minimum value) k = 1.2 for color phase = green axis (maximum value) (k always 1 when color phase not at 22.5 degrees of green axis) 0: Green Enhancement mode is disabled. 1: Green Enhancement mode is enabled.
TINTANGLE[4:0]
Tint Angle The Tint Angle is applied to the Cr and Cb values of the RGB data flow after the RGB to YCrCb conversion. The Tint Angle is coded from -20 to +20 in steps of 1.33. The bitfield is coded in 2's complement.
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STV2310 DDECCONT13
Address (hex): 13h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List Register Description
Bit 0
Bit Name
Bits[7:0) Reserved: Must be set to 0000 0000.
Function
DDECCONT14
Address (hex): 14h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved: Must be set to 0000 0000.
Function
DDECCONT15
Address (hex): 15h Reset Value (bin): 0001 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DEM_YC_DELAY[3:0]
Bit Name
Bits[7:6] Bits[5:4] DEM_YC_DELAY [3:0] Reserved. Must be set to 00. Reserved. Must be set to 01. Y vs. C Delay in Chroma Demodulator
Function
This bitfield provides a programmable Y path vs. C path delay in the Chroma Demodulator. The unit delay is a quarter of the chroma sub-carrier period. Negative values mean that the luma is in advance compared to the chroma. Bits are coded in 2's complement. 1000: -8 0000: No shift between Chroma and Luma (Default) 0111: +7
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Register List DDECCONT16
Address (hex): 16h Reset Value (bin): 0111 1010 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0 ACTITH[1:0]
SATLMTLN[1:0]
SATLMTPT[1:0]
SMHITH[1:0]
Bit Name
SATLMTLN[1:0] SATLMTPT[1:0] AGC Saturation Limit (Points/Lines)
Function
The SATLMTPT[1:0] and SATLMTLN[1:0] bits are used to program the CVBS Saturation Threshold. It is expressed as a number of samples per field (when, according to the algorithm, the number of samples is reached, the gain is decreased). The formula for the threshold computation is the following: Threshold = 1 + 4 x SATLMTPT[1:0] +16 x SATLMTLN[1:0]
SMHITH[1:0]
AGC SMHI Threshold Value This bitfield defines the Luma Low Signal Detection Threshold (when, according to the algorithm, the luma signal remains under that threshold, the gain is increased). The threshold is defined as an ADC (10 bit) code output according to the following formula: Threshold = 772 + 8 x SMHITH[1:0] (Default = 772 + 8 x 2)
ACTITH[1:0]
AGC ACTI Threshold Value This bitfield defines the Luma Saturation Threshold (when, according to the algorithm, the luma signal overtakes that threshold, the gain is decreased). The threshold is defined as an ADC (10 bit) code output according to the following formula: Threshold = 807 + 8 x ACTITH[1:0] (Default = 807 + 8 x 2)
DDECCONT17
Address (hex): 17h Reset Value (bin): 0010 0100 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STI_NB_FIELDS_CONFIRM[2:0]
Bit Name
Bit 7 Bit 6 STI_50_60HZ_ EN
Function
Reserved. Must be set to 1. Recommended value: 1 (instead of 0 at reset). Reserved. Must be set to 1. Standard ID Enable This bit modifies the standard identification algorithm. When this bit is set (default), the standard identification algorithm disregards the auto identification table entries not corresponding to the 50 or 60Hz detection performed by the synchronization block.
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STV2310
Register List
Bit Name
STI_NB_FIELDS _CONFIRM[2:0] Number of Fields to be Confirmed
Function
This bitfield operates on the second stage of the standard identification algorithm: the confirmation stage. It gives the number of consecutive fields where the standard criteria must be OK before the standard identification is confirmed. 000: 1 field 100: 8 fields 001: 3 fields (default) 101: 32 fields 010: 7 fields 110: 45 fields 011: 10 fields 111: 63 fields
SPC_OVERLOA D_OFF
Cover coefficient forced to 1 The SPC_ACC_OFF and SPC_OVERLOAD_OFF bits are related to the ACC and ACC Overload mechanisms operating on the CVBS flow. These regulating algorithms are a complement to the AGC operating on the CVBS and the Y amplitudes). The ACC and ACC Overload mechanisms operate on the chroma (C) amplitude in the CVBS flow. The ACC (automatic chroma control) operates with the Cburst burst scale factor. The ACC overload mechanism operates with the Cover chroma correction factor. Both Cburst and Cover values are internal variables. The Cover variable carries the maximum chroma value measured during the video line. 0: Cover coefficient is not forced to 1 (Overload mechanism). 1: Cover coefficient is forced to 1.
SPC_ACC_OFF
Cburst coefficient forced to 1 The Cburst variable carries the input video burst amplitude. When that amplitude is different from the standard, demodulated chroma components are scaled with Cburst. Cburst change rate and change steps are also programmable. See registers DDECCONT20[1:0] = SPC_ACC_KTHBURST[1:0] , DDECCONT20[5:4] = SPC_ACC_NB_LINEUP[1:0] , DDECCONT20[7:6] = SPC_ACC_NB_LINEDW[1:0]. 0: Cburst coefficient is not forced to 1 (ACC. mechanism). 1: Cburst coefficient is forced to 1.
DDECCONT18
Address (hex): 18h Reset Value (bin): 0101 1001 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3 NONINTER LACED_EN
Bit 2 OUT_ RANGE
Bit 1
Bit 0 COMB_ MODE
BW_SEL[2:0]
Bit Name
Bit 7 BW_SEL[2:0] Reserved. Must be set to 0. Notch Width Select
Function
This register offers the possibility to select the notch width: 000: Notch filter the narrowest 111: Notch filter the widest
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Register List
STV2310
Bit Name
NONINTERLACE D_EN Analog Output as Input Bit
Function
This bit enables the "analog output as input" mode. It is only operational when the o_vsynctype is set to the analog mode (see register o_ddeccont0[7] bit) When the o_vsynctype is set to the digital mode, that bit is irrelevant. 0: Analog Forced Interlaced Mode. The output is interlaced even if the video input is not. This is equivalent to cut 1.0. It is required by TMM. 1: Analog Output as Input Mode. The output is interlaced when the input is interlaced. The output is not interlaced when the input is not interlaced. (Default)
OUT_RANGE
Output Range Control 0: Output code range is 1 to 254 on Y, Cr and Cb outputs (Default) 1: Output code range is 16 to 235 on Y; and 16 to 240 on Cr and Cb outputs
COMB_MODE
Adaptive Comb or Notch Forced Mode This register selects the Luma Chroma Separation mode. Luma Chroma Separation can be performed by comb filtering or notch filtering. 0: Notch separation mode forced 1: Adaptive comb filter (Default)
DDECCONT19
Address (hex): 19h Reset Value (bin): 0100 0100 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved: Must be set to 0100 0100
Function
DDECCONT1A
Address (hex): 1Ah Reset Value (bin): 0010 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits[7:6] Bits [5:0] Unused. Must be set to 00. Reserved: Must be set to 10 0000
Function
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STV2310 DDECCONT1B
Address (hex): 1Bh Reset Value (bin): 1000 0100 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List Register Description
Bit 0
Bit Name
Bits[7:4] Bits[3:0] Reserved: Must be set to 1000 Reserved: Must be set to 0100
Function
DDECCONT1C
Address (hex): 1Ch Reset Value (bin): 1000 0100 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits[7:4] Bits[3:0] Reserved: Must be set to 1000 Reserved: Must be set to 0100
Function
DDECCONT1D
Address (hex): 1Dh Reset Value (bin): 1000 1000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits[7:4] Bits[3:0] Reserved: Must be set to 1000 Reserved: Must be set to 1000
Function
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Register List DDECCONT1E
Address (hex): 1Eh Reset Value (bin): 1001 1001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0
Bit Name
Bits[7:4] Bits[3:0] Reserved: Must be set to 1001 Reserved: Must be set to 1001
Function
DDECCONT1F
Address (hex): 1Fh Reset Value (bin): 0001 1000 Bit 7 DIRECTPAR ITY Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
DIRECTPARITY Direct Parity Option
Function
This bit selects the option of the direct parity on the F pad. This option is only operational when the stvddec is in the analog output mode (see register DDECCONT0[[7]). The input video parity is detected on every field. The parity issued on the FSYNC pad is normally not this direct parity but is filtered on several fields. 0: Normal parity is issued on the FSYNC pad (Default) 1: Direct parity is issued on the FSYNC pad Bit 6 Bit 5 Bit 4 Bit 3 Bits [2:1] Bit 0 Reserved: Must be set to 0. Reserved: Must be set to 0. Reserved: Must be set to 1. Reserved: Must be set to 1. Reserved: Must be set to 00. Reserved: Must be set to 0.
DDECCONT20
Address (hex): 20h Reset Value (bin): 0000 0100 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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STV2310
Register List
Bit Name
Bits [7:6] Bits [5:4] Bits [3:2] Bits [1:0] Reserved: Must be set to 00. Reserved: Must be set to 00. Reserved: Must be set to 01. Reserved: Must be set to 00.
Function
DDECCONT21
Address (hex): 21h Reset Value (bin): 0010 1011 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BLKLINE[1:0]
Bit Name
Bits[7:6] BLKLINE[1:0] Reserved. Must be set to 00. Optional output blanking lines
Function
This register provides additional blanking on lines just before or just after the vertical blanking interval. 00: no additional blanking 01: one line additional blanking 10: 2 lines additional blanking (Default) 11: 3 lines additional blanking Bits[3:0] Reserved: Must be set to 1011.
DDECCONT22
Address (hex): 22h Reset Value (bin): 1110 1000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3 HTIMECSTS EL
Bit 2
Bit 1
Bit 0 HSYNCSHIFT _EN
HSYNCSHIFT_DEL[1:0]
Bit Name
Bit 7 Bits[6:5] Bit 4 HTIMECSTSEL Reserved. Must be set to 1. Reserved. Must be set to 11. Reserved. Must be set to 0. HPLL Mode Selection
Function
0: Fixed Time Constant mode 1: Automatic mode
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Register List
STV2310
Bit Name
HSYNCSHIFT_D EL[1:0]
Function
This register allows a programmable delay of HSYNC output signal. This register is only active when o_hsyncshift_en is active (see register DDECCONT22[0]). 00: (no details yet)
HSYNCSHIFT_E N
Output Synchronisation shift enable 0: No delay (Default) 1: HSYNC is delayed with respect to the digital ouput. Note that this feature has not been decided yet.
DDECCONT23
Address (hex): 23h Reset Value (bin): 1010 1010 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:4] Bits [3:0] Reserved. Must be set to 1010. Reserved. Must be set to 1010.
Function
DDECCONT24
Address (hex): 24h Reset Value (bin): 1000 0111 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2 ERR_THRESHOLD[2:0]
Bit 1
Bit 0 PJ_EN
MAX_PJ_AMP[3:0]
Bit Name
Bits [7:4] Bits [3:1] Bit 0 Reserved. Must be set to 1000. Reserved. Must be set to 011. Reserved. Must be set to 1.
Function
DDECCONT25
Address (hex): 25h Reset Value (bin): 1001 0100 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3 HSYNC_ SAV
Bit 2
Bit 1 NOISE_THRESHOLD[2:0]
Bit 0
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STV2310
Register List
Bit Name
Bits [7:4] HSYNC_SAV Reserved. Must be set to 1001. HSYNC / SAV
Function
This option bit is active when set AND the output mode is an analog mode (see DDECCONT0[7] register). 0: the hsync signal is issued according to the analog mode description 1: the hsync signal coincidates with the SAV code in the digital flow (falling edge on SAV first byte and rising edge on SAV last byte). NOISE_THRESH OLD[2:0] HPLL Noise Threshold Selection This bitfield provides a tuning mechanism for HPLL behavior using the detected level of noise as a parameter. This bitfield defines a high noise level. When that high noise level is reached some HPLL features are disabled (phase jumps, copy protection detection). The bitfield can be considered as a cursor where an entry of 000 means that the input signal is above the high noise level, whatever the noise level detected internally. Conversely an entry of 111 means that the input signal is under the high noise level in all circumstances. Between these 2 extremes, a proportion of the detected level of noise (register DDECSTAT3) is the reference for the high noise level.
DDECCONT26
Address (hex): 26h Reset Value (bin): 0100 0100 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved. Must be set to 0100 0100.
Function
DDECCONT27
Address (hex): 1Eh Reset Value (bin): 0110 0110 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved. Must be set to 0110 0110.
Function
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Register List DDECCONT28
Address (hex): 28h Reset Value (bin): 1000 0010 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0
HUNLOCK_LINE_NUM[3:0]
HLOCK_LINE_NUM[3:0]
Bit Name
HUNLOCK_LINE _NUM[3:0]
Function
HPLL number/4 of successive err>thresh for hunlock This register is used by the HPLL. It provides the number of successive lines divided by 4 where the phase error must be above the required threshold to consider the hlock to be lost. The default value is 8 x 4 lines. HPLL number/4 of successive errHLOCK_LINE_N UM [3:0]
DDECCONT29
Address (hex): 29h Reset Value (bin): 0101 0101 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HLOCK_PH_ER_TH[3:0]
Bit Name
Bit 7 Bit 7 Bits [5:4] HLOCK_PH_ER_ TH[3:0] Reserved. Must be set to 0. Reserved. Must be set to 1. Reserved. Must be set to 01.
Function
HPLL phase error threshold / 8 for hlock / hunlock This register provides the phase error threshold for the HPLL. The same value is used for the lock and unlock mechanism. The entry value is the number of samples multiplied by 8. The default value is 5 x 8 samples.
DDECCONT2A
Address (hex): 2Ah Reset Value (bin): 1000 0010 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1 CLAMP_INT[2:0]
Bit 0
CLAMP_PROP[1:0]
CLAMP_DER[1:0]
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STV2310
Register List
Bit Name
CLAMP_PROP[1: 0] Proportional Gain Selection
Function
This register is related to the CVBS clamp regulation algorithm where a PID filter is used. CLAMP_PROP defines the Proportional Gain selection. 00: Proportional Gain divided by 64 01: Proportional Gain divided by 32 10: Proportional Gain divided by 16 11: Proportional Gain divided by 8
CLAMP_DER[1:0]
Defines the Clamp Derivate selection. 00 : 1 01 : 1/2 10 : 1/4 11 : 0
Bit 3 CLAMP_INT[2:0]
Reserved. Must be set to 0. Clamp Integral Gain Configuration This bitfield is related to the CVBS clamp regulation algorithm where a PID filter is used. This bitfield provides the integral gain selection. The entry is coded as follows: 000: Divided by 64 111: Divided by 5192
DDECCONT2B
Address (hex): 2Bh Reset Value (bin): 0110 0011 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved. Must be set to 0110 0011.
Function
DDECCONT2C
Address (hex): 2Ch Reset Value (bin): 1000 0010 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved. Must be set to 1000 0010.
Function
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Register List DDECCONT2D
Address (hex): 2Dh Reset Value (bin): 0000 1010 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0
Bit Name
Bit 7 Bit 6 Bits [5:0] Reserved: Must be set to 0. Reserved: Must be set to 0. Reserved: Must be set to 00 1010.
Function
DDECCONT2E
Address (hex): 2Eh Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: Must be set to 0. Reserved: Must be set to 0. Reserved: Must be set to 0. Reserved: Must be set to 0. Reserved: Must be set to 0. Reserved: Must be set to 0. Reserved: Must be set to 0. Reserved: Must be set to 0.
Function
DDECCONT2F
Address (hex): 2Fh Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4 OVERDRIV E_MODE
Bit 3
Bit 2
Bit 1
Bit 0
OVERDRIVE_SEL[1:0]
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STV2310
Register List
Bit Name
Bit 7 Bits [6:5] OVERDRIVE_MO DE Reserved: Must be set to 0. Reserved: Must be set to 00.
Function
This bit is used for a special proprietary mode between the STV2310 and the STV3500. It is called overdrive mode. Additional VBI data is stuffed between the EAV and the SAV to raise the output clock data. 0: Overdrive output mode disabled 1: Overdrive output mode enabled
OVERDRIVE_ SEL[1:0]
Selection of frequency shift in the overdrive mode It is only active when the overdrive mode has been selected. The n value provided by the OVERDRIVE_SEL[1:0] register will determine the number of bytes added in each preamble according to: number of bytes added = n x 32 bytes.
Bit 1 Bit 0
Reserved: Must be set to 0. Reserved: Must be set to 0.
DDECCONT30
Address (hex): 30h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bit 7 Bits [6:0] Reserved: Must be set to 0. Reserved: Must be set to 000 0000.
Function
DDECCONT31
Address (hex): 31h Reset Value (bin): 0010 0000 Bit 7 Bit 6 AGC_DIS Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVBSAGCGAIN[5:0]
Bit Name
Bit 7 AGC_DIS Reserved: Must be set to 0 Disabling AGC
Function
0: Normal mode (AGC is not disabled) 1: Test mode (AGC is disabled) Forced DAC command as specified by CVBSAGCGAIN. CVBSAGCGAIN [5:0] Forced value of CVBS AGC when in Forced Mode
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Register List DDECCONT32
Address (hex): 32h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0
Bit Name
Bits [7:4] Bits [3:0] Reserved. Must be set to 0000. Reserved. Must be set to 0000.
Function
DDECCONT33
Address (hex): 33h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bit 7 Bit [6:0] Reserved. Must be set to 0. Reserved. Must be set to 0000 0000.
Function
DDECCONT34
Address (hex): 34h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bit [6:0] Reserved. Must be set to 0000 0000.
Function
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STV2310 DDECCONT35
Address (hex): 35h Reset Value (bin): 0000 0000 Bit 7 PLLLOCKIT _EN Bit 6 RGBADJUS T_EN Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List Register Description
Bit 0
RGBADJUST[5:0]
Bit Name
PLLLOCKIT_EN PLLLOCK Pad IT Enable
Function
0: The PLLLOCK pad use is determined by the DDECCONT7 register 1: The PLLLOCK pad is used as the IT pad (in this case, register DDECCONT7 is irrelevant) RGBADJUST_EN RGB Gain Adjustment Enable 0: RGB Gain Adjustment mechanism is disabled (Default) 1: RGB Gain Adjustment enabled RGBADJUST[5:0] RGB Gain Adjustment Value This adjusts the RGB channel with the CVBS channel. The adjustment gain is expressed as [1 + RGBADJUST]. It is applied on Y, Cr and Cb when in RGB mode. It is applied on Cr and Cb in YCrCb mode. RGBADJUST is coded in 2's complement (+31 to -32). 011111: Maximum positive value of approx. +0.25 000000: RGBADJUST = 0 (Default) 100000: Maximum negative value of approx. -0.25
DDECCONT36
Address (hex): 36h Reset Value (bin): 1111 0000 Bit 7 PLLLOCK_ MASK Bit 6 VLOCK_MA SK Bit 5
Register Description
Bit 4 TVSTDID_M ASK
Bit 3
Bit 2
Bit 1 FBDEL[3:0]
Bit 0
HLOCK_MA SK
Bit Name
PLLLOCK_MASK VLOCK_MASK HLOCK_MASK TVSTDID_MASK
Function
Mask for interruption on change of PLLLOCK status Mask for interruption on change of VLOCK status Mask for interruption on change of HLOCK status Mask for interruption on change of TVSTDID status 0: Interrupt is not masked 1: Interrupt is masked
FBDEL[3:0]
delays the FB signal wrt the RGB flow The delay is coded in 2's complement (from -16 to 15) The Default value is 0, expressed in 4 x fSC clock periods.
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Register List DDECCONT37
Address (hex): 37h Reset Value (bin): 1111 1111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0
CB_SCALING[1:0]
CR_SCALING[5:0]
Bit Name
CB_SCALING [1:0] 2 LSB for Scaling Factor for Cb data flow
Function
The Cb data flow in the COR block is multiplied by the CB_SCALING factor. (Each LSB of scaling factor = 1/64) when CB_SCALING = 11 1111, the scaling factor = 1 when CB_SCALING = 00 0000, the scaling factor = 1/64
CR_SCALING [5:0]
Scaling Factor for Cr data flow The Cr data flow in the COR block is multiplied by the CR_SCALING factor. (Each LSB of scaling factor = 1/64) when CR_SCALING = 11 1111, the scaling factor = 1 when CR_SCALING = 00 0000, the scaling factor = 1/64
DDECCONT38
Address (hex): 38h Reset Value (bin): 0010 1111 Bit 7 PASSTHRO UGH_EN Bit 6 OUTBEHAV _MOD1 Bit 5
Register Description
Bit 4 OUTBEHAV _BLANK1
Bit 3
Bit 2
Bit 1
Bit 0
OUTBEHAV _BLANK2
CB_SCALING[5:2]
Bit Name
PASSTHROUGH _EN Enable for the pass-through mode
Function
The pass-through mode allows (test) lines that are sent during the Vertical Blanking interval to be sent captured by the line memory and reissued. The OUTBEHAV_MOD1 selection bit is used to block the free run mode on the output clock when there is no input video (HLOCK = 0). 0: Free run mode on the output clock when hlock = 0 (Default). The output data is blanked or not during the no video state or the transient state according to the bits OUTBEHAV_BLANK1 and OUTBEHAV_BLANK2. (See above) 1: The output clock follows the search performed by the input PLL. (This mode is mainly used for debug reasons.)
OUTBEHAV_MO D1
OUTBEHAV_ BLANK2 OUTBEHAV_ BLANK1
The OUTBEHAV_BLANK1 and OUTBEHAV_BLANK2 selection bits are used to program the STV2310 behaviour when there is no input video (HLOCK = 0) or when there is an input video (HLOCK = 1) but the vertical synchronisation is not yet acquired (VLOCK = 0). They are only operational when OUTBEHAV_MOD1 = 0. This is the normal default mode. OUTBEHAV_BLANK1 = 0, the output FIFO is read when HLOCK = 0 OUTBEHAV_BLANK1 = 1, the output data is blanked when HLOCK = 0 OUTBEHAV_BLANK2 = 0, the output FIFO is read when HLOCK = 1 and VLOCK = 0 OUTBEHAV_BLANK2 = 1, the output data is blanked when HLOCK = 1 and VLOCK = 0
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STV2310
Register List
Bit Name
CB_SCALING [5:2] 4 MSBs for Scaling Factor for Cb data flow
Function
DDECCONT39
Address (hex): 39h Reset Value (bin): 0101 0101 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved. Must be set to 0101 0101.
Function
DDECCONT3A
Address (hex): 3Ah Reset Value (bin): 0101 0101 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FRC_CLK_GEN[15:8]
Bit Name
Bits [7:0] Reserved. Must be set to 0101 0101.
Function
DDECCONT3B
Address (hex): 3Bh Reset Value (bin): 0011 0101 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved. Must be set to 0011 0101.
Function
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Register List DDECCONT3C
Address (hex): 3Ch Reset Value (bin): 1111 1100 Bit 7 VSYNCNST D_MASK Bit 6 TRICKDET_ MASK Bit 5 INTERDET_ MASK Bit 4 VCRDET_M ASK Bit 3 INSERDET_ MASK Bit 2 FBDET_MA SK Bit 1
STV2310 Register Description
Bit 0
Bit Name
VSYNCNSTD_ MASK TRICKDET_ MASK INTERDET_ MASK VCRDET_MASK
Function
Mask for interruption on change of status on VSYNCLOC_NSTD. 0: Interrupt is not masked 1: Interrupt is masked
Mask for interruption on change of status on TRICKMODE_DETECTED. 0: Interrupt is not masked 1: Interrupt is masked
Mask for interruption on change of status on INTERLACED_DETECTED. 0: Interrupt is not masked 1: Interrupt is masked
Mask for interruption on change of status on VCR_DETECTED. 0: Interrupt is not masked 1: Interrupt is masked
INSERDET_ MASK FBDET_MASK
Mask for interruption on change of status on INSER_DETECTED. 0: Interrupt is not masked 1: Interrupt is masked
Mask for interruption on change of status on FB_DETECTED. 0: Interrupt is not masked 1: Interrupt is masked
Bits [1:0]
Reserved. Must be set to 00.
5.3
VBI Control Register Descriptions
VBICONT1 Register Description
Address (hex): 3Dh Reset Value (bin): 0000 0001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SLDID[5:0] Bit 1 Bit 0
Bit Name
Bits[7:6] SLDID[5:0] Reserved. Must be set to 00. Bitfield Description
Function
DID value used by the STV2310 for coding ancillary packets. (The default value is type 2, first code reserved for 8-bit applications).
86/112
STV2310 VBICONT2
Address (hex): 3Eh Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SLFIL[5:0] Bit 1
Register List Register Description
Bit 0
Bit Name
Bits[7:6] SLFIL[5:0] Reserved. Must be set to 00. Bitfield Description
Function
Filler value used by the STV2310 for coding the filler byte in the ancillary packets. The default value is 80.
VBICONT3
Address (hex): 3Fh Reset Value (bin): 1000 0001 Bit 7 Bit 6 SLICECOM P_EN Bit 5
Register Description
Bit 4 WSTSLICIN G_EN
Bit 3
Bit 2 WSTCUSTO MFRAM
Bit 1 WSTEXTLIN ES
Bit 0 WSTALLPACK ETS
RAWFILTOF F_EN
Bit Name
Bit 7 SLICECOMP_EN RAWFILTOFF_E N Reserved. Must be set to 1.
Function
On the fly slicing level computation enable (only for TXT decoding) Hamming filtering bypass in raw mode for TXT reception 0: The filtering is active in raw mode (Default) 1: The filtering is bypassed in raw mode WST Slicing Enable 0: (WST) data slicing is disabled 1: (WST) data slicing is authorised Note that this bit is used at the top level to control the equalizer
WSTSLICING_E N
WSTCUSTOMFR AM
WST search with new framing code enable 0: The new framing code is not enabled 1: The new framing code (provided in register VBICONT4[7:0] = SLCORE[15:8]) is enabled WST extended slicing window enable 0: 1: The WST search starts at line 2
WSTEXTLINES
WSTALLPACKET S
WST slicing of all packets enable 0: Only service packets X/30 and X/31 are sampled 1: all packets are sampled
87/112
Register List VBICONT4
Address (hex): 40h Reset Value (bin): 0010 0111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0
FRAMINGCODE[7:0]
Bit Name
FRAMINGCODE[ 7:0] New Frame Code Value
Function
VBICONT5
Address (hex): 41h Reset Value (bin): 1100 0101 Bit 7 WSSF1ONL Y_EN Bit 6 VPS1ONLY_ EN Bit 5
Register Description
Bit 4
Bit 3 VPSSLICIN G_EN
Bit 2 VPSEXTLIN ES
Bit 1 WSSSLICIN G_EN
Bit 0 WSSEXTLINE S
Bit Name
WSSF1ONLY_EN VPS1ONLY_EN Bit 5 Bit 4 VPSSLICING_EN Reserved. Must be set to 0 Reserved. Must be set to 0 VPS Slicing Enable 0: (VPS) data slicing is disabled 1: (VPS) data slicing is enabled VPSEXTLINES VPS Extended Line
Function
0: VPS data is expected only in line 16 1: VPS data is expected in lines 15, 16, 17 (not necessarily all of them) WSSSLICING_E N WSS Slicing Enable 0: (WSS) data slicing is disabled 1: (WSS) data slicing is enabled WSS Extended Line 0: WSS data is expected only in line 23 1: WSS data is expected in lines 21, 22, 23, 24 (not necessarily all of them)
WSSEXTLINES
88/112
STV2310 VBICONT6
Address (hex): 42h Reset Value (bin): 0000 0000 Bit 7 Bit 6 GMVBILINE S Bit 5 GMRELAX_ EN Bit 4 GMSLICING _EN Bit 3 Bit 2 CCVBILINE S Bit 1 CCRELAX_ EN
Register List Register Description
Bit 0 CCSLICING_ EN
Bit Name
GMVBILINES GM VBI Slicing Enable
Function
0: Data slicing is active on line 21 in 60Hz and line 22 in 50Hz 1: Data slicing is authorised during the whole VBI GMRELAX_EN GEM-US Relaxed Frame Check Enable 0: Relaxed frame check is disabled GMSLICING_EN GEM-US Slicing Enable 0: Data slicing is disabled (Gem = Gemstar) CCVBILINES CC VBI Slicing Enable 0: Data slicing is running only during the line 21 in 60Hz and line 22 in 50Hz. 1: Data slicing is authorised during the entire VBI CCRELAX_EN CC Relaxed Frame Check Enable 0: Relaxed Framecheck is disabled CCSLICING_EN CC Slicing Enable 0: Data slicing is disabled 1: Data slicing is enabled 1: Relaxed Framecheck is enabled 1: Data slicing is enabled 1: Relaxed frame check is enabled
VBICONT7
Address (hex): 43h Reset Value (bin): 0000 1101 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved. Must be set to 0000 1101.
Function
VBICONT8
Address (hex): 44h Reset Value (bin): 0000 1000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1 SLHY[9:8]
Bit 0
89/112
Register List
STV2310
Bit Name
Bits [1:0] Bits [4:2] Bits [7:5] Reserved. Must be set to 00. Reserved. Must be set to 010. Reserved. Must be set to 000.
Function
VBICONT9
Address (hex): 45h Reset Value (bin): 0110 0011 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:5] Bits [4:0] Reserved. Must be set to 011. Reserved. Must be set to 0 0011.
Function
VBICONT0A
Address (hex): 46h Reset Value (bin): 0001 1100 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved. Must be set to 0001 1100.
Function
VBICONT0B
Address (hex): 47h Reset Value (bin): 0100 0110 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bit 7 Bit 6 Bit 5 Reserved. Must be set to 0. Reserved. Must be set to 1. Reserved. Must be set to 0.
Function
90/112
STV2310
Register List
Bit Name
Bits[4:3] Bit 2 Bit 1 Bit 0 Reserved. Must be set to 00. Reserved. Must be set to 1. Reserved. Must be set to 1. Reserved. Must be set to 0.
Function
VBICONT0C
Address (hex): 48h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits[7:0] Reserved. Must be set to 0001 1011.
Function
VBICONT0D
Address (hex): 49h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved: Must be set to 0001 1011.
Function
VBICONT0E
Address (hex): 4Ah Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:0] Reserved: Must be set to 0001 1011.
Function
91/112
Register List VBICONT0F
Address (hex): 4Bh Reset Value (bin): 1011 0011 Bit 7 Bit 6 CGSEW[2:0] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CGNBI[2:0]
STV2310 Register Description
Bit 0
CGNBS[1:0]
Bit Name
CGSEW[2:0] CGNBS[1:0] Interval width for the shift compansation Number of sample rate for a bit "10" for 1 sample keep every 3 CGNBI[2:0]
Function
Number of Run-in Bytes before to start CCP/GEM slice states machine
VBICONT10
Address (hex): 4Ch Reset Value (bin): 0000 1000 Bit 7 CGESPF2 Bit 6 CGESPF1 Bit 5
Register Description
Bit 4
Bit 3
Bit 2 CGVS[5:0]
Bit 1
Bit 0
Bit Name
CGESPF2 CGESPF1 CGVS[5:0] Enable the two pulse spike filter Enable the one pulse spike filter Number of sample for a bit
Function
VBICONT11
Address (hex): 4Dh Reset Value (bin): 0111 0001 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bits [7:4] Bits [3:0] Reserved. Must be set to 0111. Reserved. Must be set to 0001.
Function
92/112
STV2310 VBICONT12
Address (hex): 4Eh Reset Value (bin): 0000 1100 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List Register Description
Bit 0
Bit Name
Bit 7 Bit 6 Bits [5:0] Reserved. Must be set to 0. Reserved. Must be set to 0. Reserved. Must be set to 1100.
Function
VBICONT13
Address (hex): 4Fh Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3 WSTH[7:0]
Bit 2
Bit 1
Bit 0
Bit Name
WSTH[7:0] Hysteresis value for Teletext Slicer
Function
VBICONT14
Address (hex): 50h Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1 WSTH[9:8]
Bit 0
Bit Name
Bits[7:2] WSTH[9:8] Reserved. Must be set to 00 0011. Hysteresis value for Teletext Slicer
Function
93/112
Register List VBICONT15
Address (hex): 51h Reset Value (bin): 0001 0101 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV2310 Register Description
Bit 0
Bit Name
Bits [7:0] Reserved. Must be set to 0001 0101.
Function
VBICONT16
Address (hex): 52h Reset Value (bin): 1010 0000 Bit 7 Bit 6 EQZPRGM ODE Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EQZORDER SEL
Bit Name
Bit 7 EQZPRGMODE Reserved. Must be set to 0. 0: Coefficients set not programmable 1: Coefficients set programmable.
Function
When set, the table of coefficients can be programmed. The selection of each coefficients is done with VBI_EQUALCOEFF[2:0] EQZORDERSEL Bits [4:0] 0: Second order filter is used 1: First order filter is used Reserved. Must be set to 0 0000.
VBICONT17
Address (hex): 53h Reset Value (bin): 0101 0000 Bit 7 Bit 6 VBI_EQUALCOEFF[2:0] Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
94/112
STV2310
Register List
Bit Name
VBI_EQUALCOE FF[2:0]
Function
These bits select precomputed coefficients for the equaliser or let the equaliser select automatically the best set of coefficients or impose to the equaliser the sets of coefficients programmed 000: use set 1 of coefficients 001: use set 2 of coefficients 010: use set 3 of coefficients (central or no equaliser) 011: use set 4 of coefficients 100: equaliser in automatic mode 101: use set 5 of ceofficients 110: use programmed registers (see registers VBICONT0D and VBICONT0E) for the equaliser coefficients.
Bit 4 Bits [3:0]
Reserved. Must be set to 1. Reserved. Must be set to 0000.
VBICONT18
Address (hex): 54h Reset Value (bin): 0001 0010 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Bit 7 Bit 6 Bit 5 Bit 4 Bits [3:0] Reserved. Must be set to 0. Reserved. Must be set to 0. Reserved. Must be set to 0. Reserved. Must be set to 1. Reserved. Must be set to 0010.
Function
5.4
Acknowledge Registers
The acknowledge registers are used to acknowledge the interruption source. When ACK = 1, the IC master acknowledges the corresponding interrupt. Warning : These 2 registers can be written by the I2C but can't be read. Each bit is reset by the I2C slave (stv2310) one clock period after an high level has been detected.
DDECCONTFE
Address (hex): 7Eh - Write Only Reset Value (bin): 0000 0000 Bit 7 INTERDET_ ACK Bit 6 VCRDET_A CK Bit 5
Register Description
Bit 4 FBDET_AC K
Bit 3 PLLLOCK_A CK
Bit 2 VLOCK_AC K
Bit 1 HLOCK_AC K
Bit 0 TVSTDID_AC K
INSERDET_ ACK
95/112
Register List
STV2310
Bit Name
INTERDET_ACK VCRDET_ACK INSERDET_ACK FBDET_ACK PLLLOCK_ACK VLOCK_ACK HLOCK_ACK TVSTDID_ACK
Function
Acknowledge for interrupt on INTERLACED_DETECTED status change Acknowledge for interrupt on VCR_DETECTED status change Acknowledge for interrupt on INSER_DETECTED status change Acknowledge for interrupt on FB_DETECTED status change Acknowledge for interrupt on PLLLOCK status change Acknowledge for interrupt on VLOCK status change Acknowledge for interrupt on HLOCK status change Acknowledge for interrupt on TVSTDID status change
DDECCONTFF
Address (hex): 7Eh - Write Only Reset Value (bin): 0000 0000 Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1 VSYNCNST D_ACK
Bit 0 TRICKDET_A CK
Bit Name
Bits[7:3] Bit 2 VSYNCNSTD_AC K TRICKDET_ACK Reserved. Reserved
Function
Acknowledge for interrupt on VSYNCLOCK_NOSTD status change Acknowledge for interrupt on TRICKMODE_DETECTED status change
5.5
Status Registers
DDECSTAT1 Register Description
Address (hex): 80h - Read Only Reset Value (bin): 0001 0000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STVDDECVERS[7:0]
Bit Name
STVDDECVERS [7:0] This block is hardwired in every STV2310 cut.
Function
[7:4]: for Full Layer cuts (0001 is Cut 1.0, 0010 is Cut 2.0) [3:0]: for Metal Fix cuts
96/112
STV2310 DDECSTAT2
Address (hex): 81h - Read Only Reset Value (bin): Undefined Bit 7 VLOCK Bit 6 HLOCK Bit 5 PLLLOCK Bit 4 5060ID Bit 3 TVSTDID Bit 2 Bit 1 TVSTD[2:0]
Register List Register Description
Bit 0
Bit Name
VLOCK
Function
Flag used to signal Vertical Synchronization Signal Capture 0: Vsync is not captured 1: Vsync is captured
HLOCK
Flag used to signal Horizontal PLL (detection) lock status 0: HPLL is out of lock 1: HPLL is in lock
PLLLOCK
Flag used to signal Output PLL (line-locked) status 0: Output PLL is out of lock 1: Output PLL is in lock
5060ID
Flag used to signal detection of either 50 Hz or 60 Hz signal 0: 60 Hz signal is detected. 1: 50 Hz signal is detected.
TVSTDID
Flag used to signal that standard is identified 0: Standard is not identified. 1: Standard is identified.
TVSTD[2:0]
Identification (code) of Identified Standard See the AUTOSTD[5:0] bits in the DDECCONT1 register.
DDECSTAT3
Address (hex): 82h - Read Only Reset Value (bin): Undefined Bit 7 VSYNCLOC _NSTD Bit 6 BLANKLVL_ SHIFT_DET ECTED Bit 5
Register Description
Bit 4 DVD_DETE CTED
Bit 3 VCR_DETE CTED
Bit 2 INSER_DET ECTED
Bit 1 FB_DETEC TED
Bit 0 TRICKMOD_ DETECTED
INTERLACE D_DETECT ED
Bit Name
VSYNCLOC_ NSTD
Function
The synchronisation block normally detects the input video parity by detecting the Vsync position with respect to the Hsync. The Vsync position is normally at the beginning of line (0%) or middle of line (50%). The built-in thresholds for Vsync position are 25% and 75%. When the Vysnc is actually close to these limits, a bad parity detection may take place. This is the reason for this status bit. When set, the Vsync is positioned between 20% - 30% OR 70%-80% of input video line.
BLANKLVL_SHIF T_DETECTED INTERLACED_ DETECTED DVD_DETECTED VCR_DETECTED
When set, this bit indicates that the input video blank level is shifted during the VBI. This detection only takes place when the shift is above a determined threshold and there is a low level of noise. When set, this bit indicates that the input video is interlaced. When reset the input video is non interlaced. This bit can potentially change value at each input video field When set, this bit indicates that a DVD has been detected on the input. When set, this bit indicates that a VCR has been detected on the input.
97/112
Register List
STV2310
Bit Name
INSER_ DETECTED FB_DETECTED TRICKMOD_ DETECTED
Function
When set, this bit indicates that a transition on the FB signal has been detected inside an active line at least once in the field. This flag remains set for the next field. When set, this bit indicates that the FB signal has been detected to 1 (level detection) at least once in the field. This flag remains set for the next field. This status bit purpose is to detect special VCR playback modes where the number of lines is non standard. (note that it is not limited to VCR inputs). The standard number of lines depend on the 50Hz/60Hz detection: When in 50Hz mode, the number of lines is standard when >= 310 and <= 314 When in 60Hz mode, the number of lines is standard when >= 260 and <= 264 When this bit is set, the number of lines is non-standard.
DDECSTAT4
Address (hex): 83h - Read Only Reset Value (bin): Undefined Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NOISELVL[7:0]
Bit Name
NOISELVL[7:0]
Function
Noise level computed by sync and monitoring block
DDECSTAT5
Address (hex): 84h - Read Only Reset Value (bin): Undefined Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3 SLDID[7:0]
Bit 2
Bit 1
Bit 0
Bit Name
SLDID[7:0]
Function
Replica (read only) of bits SLDID[5:0] in register VBICONT1 with parity and checksum
DDECSTAT6
Address (hex): 85h - Read Only Reset Value (bin): Undefined Bit 7 Bit 6 Bit 5
Register Description
Bit 4
Bit 3 SLFIL[7:0]
Bit 2
Bit 1
Bit 0
98/112
STV2310
Register List
Bit Name
SLFIL[7:0] Reserved.
Function
DDECSTAT7
Address (hex): 86h - Read Only Reset Value (bin): Undefined Bit 7 Bit 6 Bit 5
Register Description
Bit 4 CC_DETEC TED
Bit 3 VPS_DETE CTED
Bit 2 WST_DETE CTED
Bit 1 WSS_DETE CTED
Bit 0 OPENLOOP
GEM_DETE CTED
Bit Name
Bit 7 Bit 6 GEM_DETECTE D CC_DETECTED VPS_DETECTED WST_DETECTE D WSS_DETECTE D OPENLOOP Reserved. Reserved. Detection of gemstar ancillary data Detection of close caption ancillary data Detection of VPS ancillary data Detection of WST ancillary data Detection of WSS ancillary data
Function
This flag indicates that the output PLL uses phase jumps for phase error correction. 0: Phase jump inactive 1: Phase jump active
99/112
Electrical Characteristics
STV2310
6
6.1
Electrical Characteristics
Absolute Maximum Ratings
Parameter
3.3 V Supply Voltage 1.8 V Supply Voltage Capacitor 100 pF discharged via 1.5 k serial resistance (Human Body Model) Operating Temperature Storage Temperature 0 - 55
Symbol
V3.3V V1.8V VESD TOPER TSTG
Min.
Typ.
Max.
3.8 2.2 4 +70 +150
Unit
V V kV C C
6.2
Thermal Data
Parameter
Junction-ambient Thermal Resistance (TQFP64, 14x14x1.4mm) two layer PCB, one copper ground layer Junction-ambient Thermal Resistance (TQFP64, 10x10x1.4mm) two layer PCB, one copper ground layer
Symbol
RthJA RthJA
Min.
Typ.
50 60
Max.
Unit
C/W C/W
6.3
Operating Conditions
Parameter
1.8 V Supply Voltage 3.3 V Supply Voltage Master Clock Frequency 1.8V Supply Current 3.3V Supply Current
Symbol
V1.8V V3.3V fMC ICC1.8V ICC3.3V
Min.
1.6 3.0
Typ.
1.8 3.3 27 235 40
Max
2.0 3.6
Unit
V V MHz mA mA
6.4
CVBS/Y/C Analog Inputs
TAMB = 25 C, VCC33 = 3.3 V, VCC18 = 1.8 V
Symbol
VIN_CVBS/Y AGC G_Step
Parameter
Y/CVBS Sync to Peak Chroma Input Voltage (Anti-Aliasing Filter with Attenuation = 0.75, Standard Color bar 100%); AGC active AGC Range on Y/CVBS inputs AGC Step
Min.
.74
Typ.
1.24 6 0.19
Max
2.08
Unit
VPP dB dB
100/112
STV2310
Electrical Characteristics
Symbol
VIN_Chroma CIN_CVBS CIN_C BWCVBS CLCVBS CBIAS ISOURCE ISINK I_Step ZIN Crosstalk
Parameter
C Full Scale Input Voltage (before external Anti-Aliasing Filter with Attenuation = 0.55) Input Coupling Capacitor for CVBS Input Coupling Capacitor for C Input Bandwidth Analog Input CVBS/Y Input Black Clamping Level C Input Bias Level Positive Clamp Current (CVBS/Y) Negative Clamp Current (CVBS/Y) I Step Clamp C Input Impedance Channel Crosstalk
Min.
0.6
Typ.
0.88 22 1 6 1.0 560
Max
1.25
Unit
VPP nF nF MHz V mV
+200 -400 5 10 50
+400 -200
A A A kOhm dB
6.5
R/G/B and Cr/Cb Inputs
Parameter
R/G/B Full Scale Input Voltage (before external Anti-Aliasing Filter with Attenuation = 0.65) R/G/B Input Clamp Level Input Coupling Capacitor Channel Bandwidth on Luma Component Channel Bandwidth on CrCb Component Cr/Cb Full Scale Input Voltage (before external Anti-Aliasing Filter with Attenuation = 0.65) Cr/Cb Clamp Level Positive Clamp Current (RGB) Negative Clamp Current (RGB) I Step Clamp +200 -400 5 50 0.5
Symbol
VIN_RGB CLRGB CIN_RGB BWRGB_L BWRGB_Chr VIN_CrCb CLCrCb ISOURCE ISINK
Min.
0.5
Typ.
0.7 1.0 22 6 3 0.7 1.3
Max
1.0
Unit
VPP V nF MHz MHz
1.0
VPP V
+400 -200
A A A dB
Crosstalk
Crosstalk between Analog Inputs
101/112
Electrical Characteristics
STV2310
6.6
FB Input
Parameter
FB Input Voltage Low Level FB Input Voltage High Level FB Input Leakage Current 1.0 1
Symbol
VIL VIH IL
Min.
Typ.
Max
0.4
Unit
V V A
6.7
Analog-to-Digital Converter (ADC)
Parameter Min. Typ. Max Unit
Symbol
10-bit ADC for CVBS Input B fCLK ED EL Analog Bandwidth ADC Clock Frequency
15 27 1 2
MHz MHz LSB LSB
Differential Linearity Error (DLE) Integral Linearity Error (ILE)
8-bit ADCs for RGB/C Inputs B fCLK ED EL Gmatch Analog Bandwidth ADC Clock Frequency Differential Linearity Error (DLE) Integral Linearity Error (ILE) RGB Gain Matching 15 27 1 2 0.5 1.5 MHz MHz LSB LSB %
6.8
Analog Reference Levels
Parameter
REFP_CVBS Pin Level Videocomm Pin Level REFP_RGB Pin Level REFM_RGB Pin Level
Symbol
REFP_CVBS Videocomm REFP_RGB REFM_RGB
Min.
Typ.
750 1.2 750 375
Max
Unit
mV V mV mV
6.9
YCrCb, Hsync, Vsync, Field and PLL Lock Outputs
Parameter
Low Level Output Voltage (IOUT = 2 mA) High Level Output Voltage (IOUT = 2 mA) Rise Time 2.4 3
Symbol
VOL VOH tr
Min.
Typ.
Max
0.4
Unit
V V ns
102/112
STV2310
Electrical Characteristics
Symbol
tf Fall Time
Parameter
Min.
Typ.
3
Max
Unit
ns
Maximum Capacitive Load
30
pf
6.10
Clock Data Output
Parameter
Low Level Output Voltage (IOUT = 4 mA) High Level Output Voltage (IOUT = 4 mA) Rise Time Fall Time Maximum Capacitive Load 2.4 3 3 30
Symbol
VOL VOH tr tf
Min.
Typ.
Max
0.4
Unit
V V ns ns pf
6.11
CLKSEL, TST_MODE, NRESET and I2CADD Inputs
Parameter Min. Typ. Max Unit
Symbol
CLKSEL Input VIL VIH IL
CLKSEL Input Voltage Low Level CLKSEL Input Voltage High Level CLKSEL Input Leakage Current 1.2
0.6
V V
1
A
TST_MODE, NRESET and I2CADD Inputs VIL VIH IL Input Low Level Input High Level Input Leakage Current 2.0 -1.0 1.0 0.8 V V A
6.12
Main Clock Characteristics
Parameter Min. Typ. Max Unit
Symbol
Differential Clock Input (CLKXTM, CLKXTP) FS FS_TOL Duty_cycle VIL VIH IL Nominal Frequency Tolerance (including Temp. shift) Clock Duty Cycle Input Voltage Low Level Input Voltage High Level Input Leakage Current 1.2 1 A 45 27 50 50 0.6 MHz ppm %
External Crystal Characteristics
103/112
Electrical Characteristics
STV2310
Symbol
fXTAL RBIAS
Parameter
Crystal Frequency, Fundamental Mode Internal Bias Resistance Tolerance (including Temp. shift)
Min.
Typ.
27 1.5
Max
Unit
MHz M
60
ppm
104/112
STV2310
Electrical Characteristics
6.13
Horizontal/Vertical Synchronization Block
Parameter
Output Luma/Sync Misalignment Output Chroma/Sync Misalignment Line PLL Capture Range
Symbol
Min.
Typ.
Max
2.5 20 8
Unit
ns ns %
6.14
Chroma Block
Parameter
ACC Control Range Chroma PLL Capture Range Total Chroma Phase Tracking Error Quadrature Error Hue Control Range Hue Control Step 1.5
Symbol
Min.
-6 0.8
Typ.
Max
+30 1
Unit
dB kHz deg. deg. deg deg.
0.5 0.5
1 1 40
6.15
IC Bus Characteristics
Parameter Test Conditions Min. Typ Max. Unit
Symbol
SCL VIL VIH IIL fSCL tR tF CI SDA VIL VIH IIL tR tF VOL tF
Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance 1 V to 2 V 2 V to 1 V VIN = 0 to 5.0 V
-0.3 2.3 -10
1.5 5.5 10 400 300 300 10
V V A kHz ns ns pF
Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time VIN = 0 to 5.0 V 1 V to 2 V 2 V to 1 V IOL = 3 mA 2 V to 1 V
-0.3 2.3 -10
1.5 5.5 10 300 300 0.4 250
V V A ns ns V ns
105/112
Electrical Characteristics
STV2310
Symbol
CL CI IC Timing tLOW tHIGH tSU,DAT tHD,DAT tSU,STO tBUF tHD,STA tSU,STA
Parameter
Load Capacitance Input Capacitance
Test Conditions
Min.
Typ
Max.
400 10
Unit
pF pF
Clock Low period Clock High period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low to High Transition
1.3 0.6 100 0 0.6 1.3 0.6 0.6 900
s s ns ns s s s s
Figure 19: IC Bus Timing
SDA
tBUF tLOW tSU,DAT
SCL tHD,STA tR tHD,DAT tHIGH tF tSU,STO
SDA
tSU,STA
Note:
The STV2310 device can be interfaced with +3.3 V or +5.0 V logic levels.
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STV2310
Package Mechanical Data
7
7.1
Package Mechanical Data
TQFP64 14x14 Package Figure 20: TQFP64 14x14 Package
Figure 21: 64-Pin Thin Quad Flat Package
0.10mm .004 seating plane
Dim. A A1 A2 B C D D1 D3 E E1 E3 e K L L1 N
Millimeters
Min. Typ. Max. Min.
Inches
Typ. Max.
L1
L
K
1.60 0.05 0.15 0.002 1.35 1.40 1.45 0.053 0.055 0.30 0.37 0.45 0.012 0.015 0.09 0.20 0.004 16.00 0.630 14.00 0.551 12.00 0.472 16.00 0.630 14.00 0.551 12.00 0.472 0.80 0.031 0 3.5 7 0.45 0.60 0.75 0.018 0.024 1.00 0.039 Number of Pins 64 ND 16 NE
0.063 0.006 0.057 0.018 0.008
0.030
16
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Package Mechanical Data
STV2310
7.2
TQFP64 10x10 Package Figure 22: TQFP64 10x10 Package
Figure 23: 64-Pin Thin Quad Flat Package
0.10mm .004 seating plane
Dim.
A A1 A2 b C D D1 E E1 e K L L1
Millimeters
Min. 0.05 1.35 0.17 0.09 Typ. Max. 1.60 0.15 1.45 0.27 0.20 Min.
Inches
Max. 0.063 0.002 0.006 0.053 0.055 0.057 0.007 0.009 0.011 0.004 0.008 0.472 0.394 0.472 0.394 0.020 0 3.5 7 0.018 0.024 0.030 0.039 16 NE 16 Typ.
1.40 0.22
L1
L
N
K
12.00 10.00 12.00 10.00 0.50 0 3.5 7 0.45 0.60 0.75 1.00 Number of Pins 64 ND
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STV2310
Revision History
8
Revision History
The following table summarizes the modifications applied to this document.
Revision
1.0 1.1 1.2 1.3 First Issue Addition of Section Addition of Chapter
Description
Date
N/A
5.3: VBI Control Register Descriptions on page 86. 7: Package Mechanical Data on page 107.
March 2001 March 2001 9 May 2001
Addition of Section 4.5: Standard Research Sequence Programming on page 21, Section 4.9: Output Scaler and Format Converter on page 24, Section 4.3: Input Sample Rate Conversion on page 18 and Section 6: Electrical Characteristics on page 100 Update of all register descriptions, general descriptions and programming information. Pin description section reformatted. Addition of Anti-Aliasing Filter Diagrams. Update of all register descriptions, general descriptions and programming information. Update of Figure
1.4 1.5 1.6 1.7
June 2001 July 2001 July 2001 November 2001
9 and Analog Input Stage programming data.
Reset values corrected in Register Descriptions and register DDECCONT35 updated with Cut 2 information. Section 6: Electrical Characteristics on page 100 updated. Figure 35 and Figure 35 updated. Moved to Datasheet template 2.1 and converted from single file to book format. Updated Figure 18 on page 30 and Figure 3 on page 8, Zoom in/out function characteristics clarified. Addition of ESD PERFORMANCES on page 80. SECAM filter is removed. Registers DDECCONT2A, DDECCONT17 and DDECCONTE modified. Update of Section
1.8
1.9
12 February 2002
2.0 2.1 2.2 2.3 2.4
6: Electrical Characteristics on page 100.
25 March 2002 10 July 2002 21 Nov 2002
ESD Section removed. Pin NRESET changed to NRESET. Updated register information for cut 3.0. Updated Figure
3 on page 8 and Figure 6 on page 15.
20 January 2003
Updated Figure 3 on page 8 and Figure 4 on page 9. Update to VCC33OUT in Section 2.2: Pin Descriptions. Update of Figure 6 on page 15. Ouput Sync Pulse information added to Section 4.2: Synchronization and Monitoring Unit on page 16. Update of Section 4.4: Luminance and Chrominance Separation on page 19. Update of Table 8: Confirmation Codes on page 22. New section added: Section 4.6: Standard Identification on page 22. Update of Section 4.7: Chroma Demodulation on page 22. Update of Section 4.8: Soft Mixer on page 23.Update of Section 4.12: Output FIFO and Line-locked Ouput Pixel Clock Generator on page 29. GDIFF added to Section 6.7: Analog-to-Digital Converter (ADC) on page 102. Updated Figure 35: Notch Filter - Narrow Group on page 135 and Figure 36: Notch Filter - Wide Group on page 136.
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Revision History
STV2310
Revision
3.0
Description
Re-organisation and update of page 1 and page 2. Modification of text in Section 1: General Description on page 6. Updated Figure 2 on page 7, Figure 3 on page 8 and Figure 4 on page 9. Modification of pin descriptions in Section 2: Pin Allocation and Description on page 9. Addition of Section 3: Default Setup At Reset on page 13. Major updates to Chapter 5: Register List on page 80. Major change to Figure 6 on page 15. Various modifications to Chapter 6: Electrical Characteristics on page 134. Addition of TQFP64 10x10 package in Chapter 8: Package Mechanical Data on page 143. Minor updates to Register Description
Date
July 2004
3.1
December 2004
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STV2310
Index
A
A/D Converter ................................................ 6, 15 Adaptive Time Constant .................................... 16 Alpha Blending .................................................. 23 Anti-Aliasing Filter .............................................. 15 Automatic Flesh Control .................................... 23 Automatic Gain Control ...................................... 14
I
IC Bus Interface .................................................. 1 Input Sample Rate Converter ............................ 18
M
Mixing Slope ...................................................... 23
C
CCIR Specification ................................... 6, 24, 41 Chroma Demodulator ...................................21-22 Clocks Pixel ............................................................... 7 System ..................................................... 6, 18 Clocks System ................................................... 16 Color Kill Control ................................................ 66 Comb Filter .......................................................... 1
O
Output Pixel Clock Frequency ........................... 40 Output Sample Rate Converter ......................... 24
P
Panorama Mode ................................................ 27 Programmable Gain Amplifier ............................ 14
F
Fast Blanking ..................................................... 23 Filtering Comb ........................................................... 19 Notch ........................................................... 19 Flesh Tone Correction ....................................... 23 Flesh Tone Reference Angle ............................. 67 Free-running Mode ............................................ 16
S
Skew Extraction ................................................. 16 Soft Mixer ........................................................... 23 Square Pixel Mode ............................................ 26 Standard Identifier ............................................. 21 Synchronization Slicer ....................................... 16
T
Tint Angle Correction ......................................... 28 Tint Control ........................................................ 28
G
Green Enhancement ......................................... 68
V
VBI Data Slicer .................................................. 41 Vertical Blanking Interval ................................... 29 Vertical Sync Processor ..................................... 16
H
Horizontal PLL ................................................... 16 Hue Control ....................................................... 22 Hue Levels ......................................................... 28
XYZ
Zoom-In Mode ................................................... 26 Zoom-Out Mode ................................................. 27
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STV2310
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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